In stm32h743, in SPI, enabling the EOT IRQ after the other IRQs are enabled makes the SPI ISR to be fired endlessly. Why?

[DGast.1]

In stm32h743, in SPI, I have a slave device with interrupts enabled. In particular, I'm enabling all the error interrupts (UDR, OVR, CRCERR, FRE, MODF), and the RXP, TXP and EOTIE interrupts, in that order.

If I enable EOTIE the first of all of them, everything goes fine. If I enable it after the TXP (as above), the SPI ISR gets fired endlessly. I read the SR reg. within it and its value is 0x12 (TXTF and TXP set), which makes sense because I didn't fill the TxFIFO, but I don't see why it fires all the time.

Any idea why this happens?

[FBL]

Hello @DGast.1​,

> If I enable it after the TXP (as above) 

I think the screenshot you intended to share is still not attached.

Would you mind adding it for better understanding?

Thanks

[DGast.1]

Sorry, I meant if I enable it as I explained above, that is, after TXP. It's difficult to add the code to explain it as it is enabled within a RTOS' driver.

[Pavel A.]

> Any idea why this happens?

The ISR will be re-entered immediately again while the interrupt source is active and unmasked (and the whole peripheral's interrupt is enabled in NVIC). This is how NVIC works.

Duplicate:

https://community.st.com/s/question/0D53W00002CJMvdSAH/in-stm32h743-is-the-txp-interrupt-fired-endlessly-until-the-tx-fifo-is-full

[FBL]

As mentioned by Pavel, you should follow the sequence.

Here is another thread about the same topic SPI EOT interrupt triggered right after SPI enable (st.com)