Is there an example of dual simultaneous ADCs for the STM32H5?

[Andrei Chichak]

Using NUCLEO-H563ZI, FW_H5 V1.3.0, CubeIDE 1.16.0, MacOS 14.5.

I've been beating my head against the wall, getting some test code going.

4 ADC channels, 2 on ADC1, 2 on ADC2.

Conversions triggered by timer 3. (200 groups of 4 conversions per second)

Results delivered using DMA.

I've done this before with F4s and F7s, but the H5 is kicking my butt and the example code set for the H5 is incomplete and doesn't have an ADC sample similar to this so far.

I've put together an IOC file and generated code with no changes from the generated code, and when that code initializes ADC2, the error handler gets called when HAL_ADCEx_MultiModeConfigChannel fails after a call to ADC_MULTI_SLAVE. I'm not sure what it's doing, but I must be missing something in the IOC model since it can't get through the init code.

Is there a working example of dual simultaneous for the H5s, or a processor like the H5s that uses the GPDMA unit, or what am I missing in my IOC file?

Thanks,

Andrei from The Great White North

[AScha.3]

Hi,

just to understand: 200 groups of 4 conversions per second -> so you want just 4 conversions per second or 800 ?

And why then dual simultaneous ADC and DMA ?

Just for fun, to make it as complicated as possible and to test it - or why ?

[Andrei Chichak]

No, you misunderstand.

It's 800 per second. This is just a test program. I usually deal with about 14 channels, which would be 2800 samples per second. But I was just trying to figure out how to get a minimal scanning (more than one channel per ADC) simultaneous (more than one ADC) DMA project going at all. As soon as I try enabling the second ADC, the CubeMX generated init code fails, it doesn't even get to my code.

I use dual simultaneous because some of the channels have to be measured simultaneously, like measuring the voltage and current of the same signal to get power. If the signal varies (sinusoidal) or if the samples are not near enough together, they are not measuring the same signal.

I also trigger the ADCs using a timer so that the samples are EXACTLY n ms. apart. The people that I work with are engineers and physicists, so having the timing vary - even slightly - goes against their retentive nature.

There are samples for the F4 called ADC_TripleModeInterleaved that shows this quite well, but using three ADCs since the F4 has three.

[nouirakh]

Hello @AScha.3 

I don’t think there is simultaneous/DMA exmple for H5, I’ll take a look at your IOC configurations and let you know what I find.

[Andrei Chichak]

Thank you @nouirakh. I have not been able to find an existing example, but I'm also not sure which other processor families use the H5 style DMA IP.

[nouirakh]

Hello @Andrei Chichak 

This is a CubeMX generation problem, CubeMX calls HAL_ADCEx_MultimodeConfigChannel in the ADC2 config while this function should only be called with the ADC master (ADC1).

The blue box function must therefore be removed:

[Andrei Chichak]

Okay, that works.

It took a while to get everything working. This is what I learned:

1) You only use one DMA channel, set for ADC1, for both ADCs. Don't setup a second DMA channel for ADC2.

2) The results will be returned interleaved, like |ADC1ADC2|, so the two 16-bit results are bundled into a word. Use a word sized transfer. According to the docs at the start of the function, the length specified in the third parameter of HAL_ADCEx_MultiModeStart_DMA is supposed to be in bytes, but you get four times that amount. So for a 2-channels from 2-ADCs of 16-bit transfer x 2 for ping-pong, you'd expect the length to be 16 bytes, but you specify a length of 4. Maybe the parameter is supposed to be the number of words in a half transfer???

3) I get a hard fault in the DMA completion functions, accessing the results array, if any I-cache is turned on. This was not obvious since I'm transferring from a device to SRAM and running from FLASH, not SRAM, so I didn't expect that the I-cache would be involved. If I disable ICACHE, no more hard fault.

- followup on (3), I was converting Vref and according to https://community.st.com/t5/stm32-mcus/how-to-avoid-a-hardfault-when-icache-is-enabled-on-the-stm32h5/ta-p/630085, there is an issue 

A