Issue with MPU setup in LwIP_HTTP_Server_Netconn_RTOS for F7 V1.17.0

[Andrei Chichak]

In LwIP_HTTP_Server_Netconn_RTOS, MPU_Config has three sections:

1) Mark the complete 4GB memory map as shareable, non-cacheable, and non-bufferable.

2) Create a 16kB area starting at 0x20078000 for ethernet buffers, non-sharable, non-cacheable, non-bufferable

3) Create a 1kB area starting at 0x2007C000 for ethernet descriptors, shareable, non-cacheable, bufferable

First, is #1 actually needed?

Second, #2 says that it is in SRAM2, but it is actually in SRAM1. SRAM2 doesn't start until 0x2007C000. The size makes me think that it should be marking all of SRAM2, but the base address is wrong. Having the region start at 0x20078000 for 16k will mark the top 4k of SRAM1 and the bottom 12k of SRAM2. An odd choice or a bug?

#3 could actually be correct, but wastes a lot of memory for 2*0xA0 == 320 bytes of space.

Finally, the symbol __estack is created in the linker file that points at 0x20080000, the top of SRAM2. But under this address is the ethernet buffers in SRAM2. This would cause some weird stack corruption as the ethernet DMAs stuff into the stack area. I think __estack should be set to 0x2007C000 which would be the top of SRAM1, under the ethernet buffers.

So, what are the implied rules in place for ethernet? It apparently needs a non-cacheable region for ethernet descriptors. There seems to be a need for ethernet buffers, but no support in the code that I can find. And why would the whole 4GB memory map be non-cacheable and non-bufferable? Is this the default?

Waiting for the next firmware release for F7,

Andrei

[Andrei Chichak]

I came here to ask this set of questions again, 3 months later, and forgot that I asked them before. Thank you, previous me, for reminding me of a few fine details.

Update; I also figured out that the complete 4GB address space is being marked as execute-never. An odd choice considering that the FLASH where the code is being stored should be marked as execute-never. How does it execute? Enquiring minds want to know.

Going through AN4838 and the sample code for the H7 family version leads me to believe that LwIP_HTTP_Server_Netconn_RTOS for F7 is broken wrt the MPU, but there is no documentation that would indicate what the original author was trying to achieve and what constraints they were working around, but I guess the code works at some level, so the code didn't trip any enabled exception handlers.

Could someone at ST that has knowledge of the F7 ethernet peripheral and MPU take a look at the MPU setup code in this project and give a rundown of what the three region definitions are doing?

Thanks,

Andrei

[Piranha]

1) That region is created to solve the issue described in this topic. And it doesn't apply to all 4 GB range, because it sets subregion disable bits.

2) ST uses it by defining LWIP_RAM_HEAP_POINTER for lwIP heap. Indeed it is actually at the end of SRAM1, but it doesn't cross into SRAM2. Your math is wrong: 0x20078000 = 0x2007C000 - 16K. The necessity of this is just a direct consequence of their incompetent "developers" being incapable of correctly doing this: "Maintaining CPU data cache coherence for DMA buffers".

3) I can add that there is absolutely no point in creating two separate memory sections and regions for Rx and Tx descriptors.

For stack pointer even better better placement is at the end of DTCM. And, of course, DTCM must not be merged with SRAM. More details in your other topic.