LTDC pins slew rate in device tree [Zephyr]

[xavierpacheco-eaton]

While looking at the stm32h745xihx-pinctrl.dtsi file I see the slew rate is defined for the QUADSPI pins, but the LTDC pins. Is it set to Very High speed implicitly? I would be concerned if they are set to Low Speed by default.

 

Thanks in advance for any input.

[Sarra.S]

Hello @xavierpacheco-eaton, 

According to the STM32H745 datasheet, in the LTDC paragraph, the output speed is OSPEEDRy[1:0] = 11, which corresponds to very-high-speed configuration, and the high LTDC clock output frequency (up to 150 MHz), so, the slew rate needs to be set appropriately explicitly to handle these high-speed signals and to avoid concerns about the default configuration potentially being set to a lower speed. 

 

/omit-if-no-ref/ ltdc_de_pk7: ltdc_de_pk7 {
 pinmux = <STM32_PINMUX('K', 7, AF14)>;
 slew-rate = "very-high-speed"; // Explicitly setting the slew rate
};

 

 Hope that answers your question!