Mid-byte SPI transfer detection

[badaboum5]

Hello,

This is assuming STM32G0 with SPI configured as slave.

 

I'm looking for a way to detect if a ongoing SPI transfer is happening. Not at the byte level but at the bit level.

So I can detect if some incomplete byte is pending in the RX buffer (due to a faulty clock signal).

Is there a simple way / bit for that in the SPI registers? Maybe I don't use the correct phrasing but I could not find anything about it. BSY is for a multi-byte transfer afaik.

 

Also, can someone confirm that when the CS is toggled, it does trash the incomplete byte received and start clean for next byte to be received. That would make sense.

 

Much appreciated, thank you,

[TDK]

The typical way would be to check if CS is low. This can be done even if it's configured as an AF pin. But this leads to a race condition as a bit may be shifted after you read it and before you do whatever you're doing in response.

Setting an interrupt for a rising CS edge can allow the slave to get ready for the next transaction with minimal delay. Lots of slave SPI devices have a requirement that CS must remain high for a certain amount of time between transactions because of this synchronization method.

If CS goes high before end of the word, the shift register is discarded. When it's asserted again, a new word starts.

 

[badaboum5]

The CS use is ideal but I must also handle the case without it (CS/MOSI/CLK is controlled by software on another board, I can't exclude a bad implementation). I could also use timers to generate a timeout too.

I'll check SPI registers for a flag in the HAL declarations, maybe it exists somewhere.

Thank you