Missing SCB (System Control Block) Peripheral Definition in STM32H533.svd File

[mani9989]

Hella All, 

While working with the STM32H533RE microcontroller and using VS Code with PlatformIO for debugging, I noticed that the SCB (System Control Block) peripheral definitions appear to be missing from the SVD file.

 

The SCB is a critical ARM Cortex-M33 core peripheral that should include registers such as:

• CPUID (CPU ID Base Register) - 0xE000ED00
• ICSR (Interrupt Control and State Register) - 0xE000ED04
• VTOR (Vector Table Offset Register) - 0xE000ED08
• AIRCR (Application Interrupt and Reset Control Register) - 0xE000ED0C
• SCR (System Control Register) - 0xE000ED10
• CCR (Configuration and Control Register) - 0xE000ED14
• And other SCB registers in the 0xE000E000-0xE000EFFF address range

 

The missing SCB definitions limit our ability to:

• Monitor system control registers during debugging
• Analyze interrupt and exception behavior
• Debug power management and system configuration issues
• Perform comprehensive system-level debugging

 

I would greatly appreciate your assistance in resolving this issue.

 

Best Regards,

ManiK

[STTwo-32]

Hello @mani9989 

We no longer support MCU core registers in our SVD files as they can be part of the IDE in use (IAR,Keil,CubeIDE, etc...).

It did create confusion in the past weather the user is using the MCU register's view integrated in the IDE or from SVD file, so we are now sticking to supporting only IPs related to STM32 products in our SVD files.

Best Regards.

STTwo-32

[mani9989]

Hello @STTwo-32,

Thank you for the clarification.

Since SCB and other core registers are not included in the SVD file for STM32H5, could you please advise on the best way to access or monitor SCB registers (e.g., VTOR, AIRCR, ICSR) during debugging in VS Code with PlatformIO?

Specifically, I'm looking for guidance on:

1. How to inspect SCB register values during a debug session (e.g., trap cause, exception entry).

2. Recommended approach to capture trap/exception information like:

   • HardFault status (HFSR)

   • Configurable Fault Status (CFSR)

   • Bus Fault (BFAR)

   • MemManage Fault (MMFAR)

3. Any suggestions for manual mapping or watch expressions in the debugger that would allow me to monitor these registers, since they’re not shown in the peripheral view.

Any tips or best practices for bare-metal Cortex-M33 debugging without full SVD support would be greatly appreciated.

Best regards,
Manikanta 

[STTwo-32]

Hello @mani9989 

This is a new question. So, you may create a new post for it (after selecting a best answer for this post) so your question have more visibility and more people may help you (ST experts and other community members).

Best Reagrds.

STTwo-32

[mani9989]

I raised this as a new topic thank you