Nucleo-H563ZI PLL1 won't lock in

[Matze02]

Hey all,

i need to use the Rust Programming Language. Now i want to enable the PLL to increase the system srequency.

I'm using the "stm32h5" crate (https://crates.io/crates/stm32h5).

 

 

let dp = stm32h563::Peripherals::take().unwrap(); // Setup handler for device peripherals
 let rcc = dp.RCC;

 dp.FLASH.acr().write(|w| unsafe {
 w.latency().bits(5);
 w.prften().set_bit()
 });

 dp.PWR.voscr().write(|w| w.vos().bits(0b11)); //VOS scale 1
 while dp.PWR.vossr().read().vosrdy().bit() != true {}

 dp.ICACHE.cr().write(|w| w.en().set_bit());

 rcc.cr().write(|w| w.hsebyp().set_bit());
 rcc.cr().write(|w| w.hseon().set_bit()); //Enable High speed external clock 8 MHz
 while rcc.cr().read().hserdy().bit_is_clear() {}
 rcc.cr().write(|w| w.hseext().set_bit());

 //PLL1
 rcc.cr().write(|w| w.pll1on().clear_bit());
 while rcc.cr().read().pll1rdy().bit_is_set() {}

 rcc.pll1cfgr().write(|w| w.pll1src().bits(0b11)); //HSI as PLL1 source
 rcc.pll1cfgr().write(|w| unsafe { w.pll1m().bits(4) }); //'16' for HSI
 rcc.pll1divr()
 .write(|w| unsafe { w.pll1n().bits(249).pll1p().bits(1).pll1q().bits(1) }); //250 MHz

 rcc.pll1fracr().write(|w| w.pll1fracn().bits(0));
 rcc.pll1cfgr().write(|w| w.pll1fracen().set_bit());

 rcc.pll1cfgr().write(|w| w.pll1rge().bits(0b01)); //input frequency range 2 MHz to 4 MHz
 rcc.pll1cfgr().write(|w| w.pll1vcosel().clear_bit()); //output frequency wide VCO range

 rcc.pll1cfgr().write(|w| w.pll1pen().set_bit());
 rcc.pll1cfgr().write(|w| w.pll1qen().set_bit());

 rcc.cr().write(|w| w.pll1on().set_bit());
 while rcc.cr().read().pll1rdy().bit_is_clear() {} //Stuck here

 

Does anybody know, what i'm doing wrong? Coudn't find any solutions so far.

Thanks

[Matze02]

The command in line 23 is wrong. The HSE is the source, but the bits are right

[krotti42]

Why are you enabling the fractional mode, when you program the integer mode (RCC_PLL1DIVR) from the PLL?

rcc.pll1fracr().write(|w| w.pll1fracn().bits(0));
 rcc.pll1cfgr().write(|w| w.pll1fracen().set_bit());

The initialization flow according the TRM:

[Matze02]

Hey Krotti42, thanks for your message.

I need the PLL for the FDCAN peripheral. For that i found an example here https://github.com/STMicroelectronics/STM32CubeH5/tree/main/Projects/NUCLEO-H563ZI/Examples/FDCAN

/*-------------------------------- PLL1 Configuration -----------------------*/
 /* Check the parameters */
 assert_param(IS_RCC_PLL(pOscInitStruct->PLL.PLLState));

 if ((pOscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 {
 /* Check if the PLL1 is used as system clock or not */
 if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 {
 if ((pOscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 {
 /* Check the parameters */
 assert_param(IS_RCC_PLL1_SOURCE(pOscInitStruct->PLL.PLLSource));
 assert_param(IS_RCC_PLL1_DIVM_VALUE(pOscInitStruct->PLL.PLLM));
 assert_param(IS_RCC_PLL1_MULN_VALUE(pOscInitStruct->PLL.PLLN));
 assert_param(IS_RCC_PLL1_DIVP_VALUE(pOscInitStruct->PLL.PLLP));
 assert_param(IS_RCC_PLL1_DIVQ_VALUE(pOscInitStruct->PLL.PLLQ));
 assert_param(IS_RCC_PLL1_DIVR_VALUE(pOscInitStruct->PLL.PLLR));

 /* Disable the PLL1. */
 __HAL_RCC_PLL1_DISABLE();

 /* Get Start Tick*/
 tickstart = HAL_GetTick();

 /* Wait till PLL1 is disabled */
 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
 {
 if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
 {
 return HAL_TIMEOUT;
 }
 }

 /* Configure the PLL1 clock source, multiplication and division factors. */
 __HAL_RCC_PLL1_CONFIG(pOscInitStruct->PLL.PLLSource,
 pOscInitStruct->PLL.PLLM,
 pOscInitStruct->PLL.PLLN,
 pOscInitStruct->PLL.PLLP,
 pOscInitStruct->PLL.PLLQ,
 pOscInitStruct->PLL.PLLR);

 assert_param(IS_RCC_PLL1_FRACN_VALUE(pOscInitStruct->PLL.PLLFRACN));

 /* Disable PLL1FRACN . */
 __HAL_RCC_PLL1_FRACN_DISABLE();

 /* Configure PLL PLL1FRACN */
 __HAL_RCC_PLL1_FRACN_CONFIG(pOscInitStruct->PLL.PLLFRACN);

 /* Enable PLL1FRACN . */
 __HAL_RCC_PLL1_FRACN_ENABLE();

 assert_param(IS_RCC_PLL1_VCIRGE_VALUE(pOscInitStruct->PLL.PLLRGE));

 /* Select PLL1 input reference frequency range: VCI */
 __HAL_RCC_PLL1_VCIRANGE(pOscInitStruct->PLL.PLLRGE) ;

 assert_param(IS_RCC_PLL1_VCORGE_VALUE(pOscInitStruct->PLL.PLLVCOSEL));

 /* Select PLL1 output frequency range : VCO */
 __HAL_RCC_PLL1_VCORANGE(pOscInitStruct->PLL.PLLVCOSEL) ;

 /* Enable PLL1 System Clock output. */
 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVP);

 /* Enable the PLL1. */
 __HAL_RCC_PLL1_ENABLE();

 /* Get Start Tick*/
 tickstart = HAL_GetTick();

 /* Wait till PLL1 is ready */
 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
 {
 if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
 {
 return HAL_TIMEOUT;
 }
 }
 }

And here they used the fractional value = 0 (as you can see in line 49). So i thought i could give it a try, but still won't work. Now I deleted this 2 lines out of my code, but noting changed.

 

[Guillaume K]

Hello

If I understand correctly, you are using directly the STM32H5 Peripheral Access Crate because there is not yet an STM32H5 Rust HAL that provides high level clock configuration functions ?

The STM32H5 Rust HAL is very new and under development. There may be ongoing pull requests on the github project that could give you hints, even if they are not yet officially merged in a HAL release:

rcc: Calculate PLL clocks and implement core clock configuration logic by astapleton · Pull Request #13 · stm32-rs/stm32h5xx-hal · GitHub

examples: Add rcc and fractional-pll examples by astapleton · Pull Request #15 · stm32-rs/stm32h5xx-hal · GitHub

 

Guillaume