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J
Jack3
Graduate II
May 24, 2024
Solved

NUCLEO-H755 - ETH configured (Non-RTOS) but LWIP remains grayed out

  • May 24, 2024
  • 2 replies
  • 1883 views

Hi STM32 friends,

I'm about to learn something new, because I hit a problem with STM32CubeMX 6.11.1 (newest)
I have used Ethernet on several M7 platforms, not always without a bit of struggling.
However, this time after configuring ETH, LWIP remains grayed out.
I'm using a NUCLEO-H755ZI-Q, which has an M4 and M7 core. I use the M7 core for ETH.
There are no warnings at the ETH configuration, except:
"The ETH can work only when RAM is pointing at 0x24000000"
So I modified the First Tx Descripter Address to 0x24000200, and First Rx Descripter Address 0x24000000.
(I guess they were wrong at first: 0x30000200 and 0x30000000)
The warning remains nevertheless.
The problem is LWIP remains grayed out.
The M7 DCache is enabled (as well as the ICache).

I configured the MPU:

Region 0:
Address: 0x24000200
Size: 16KB
SubRegion: 0x0
TEX: level 1
Access: ALL ACCESS PERMITTED
Instruction: ENABLE
Shareability: ENABLE
Cacheability: DISABLE
Bufferable: DISABLE

Region 1:
Address: 0x24000000
Size: 256B
SubRegion: 0x0
TEX: level 0
Access: ALL ACCESS PERMITTED
Instruction: ENABLE
Shareability: ENABLE
Cacheability: DISABLE
Bufferable: ENABLE

I'm not using RTOS here (as in previous projects, where it worked).

LWIP reports:
Status: Not available: Active only if: ETH IP configured / FREERTOS is enables when MBEDTLS is enabled.
I understand from this that only having ETH IP configured should be sufficient, as I don't use MBEDTLS.
ETH IP is configured. I don't use FREERTOS and MBEDTLS.

What can cause this problem that LWIP remains grayed out?

I attached my ios file, to make playing around easy.
I hope somebody has seen this or knows the solution.
Thank you very much for helping out!

Note: I didn't find the "ETH" label to add for this post.

    This topic has been closed for replies.
    Best answer by STea

    Hello @Jack3 ,

    indeed, after examining you ioc file which was generated with MX v6.11.0 (not the latest 6.11.1),i'm able to reproduce you issue as a quick workaround you can select booth cortex M4 and M7 in the assign section for LwIP and then you can configure LwIP with CM7 only.

    this issue was reported internally as needing more investigation:

    internal ticket number 182330 (This is an internal tracking number and is not accessible or usable by customers)

    BR

    2 replies

    S
    STeaAnswer
    ST Employee
    May 24, 2024

    Hello @Jack3 ,

    indeed, after examining you ioc file which was generated with MX v6.11.0 (not the latest 6.11.1),i'm able to reproduce you issue as a quick workaround you can select booth cortex M4 and M7 in the assign section for LwIP and then you can configure LwIP with CM7 only.

    this issue was reported internally as needing more investigation:

    internal ticket number 182330 (This is an internal tracking number and is not accessible or usable by customers)

    BR

    J
    Jack3Author
    Graduate II
    May 24, 2024

    Thank you very much! That makes the difference.
    I just wanted to add LWIP manually to the project, but I like this solution, because I think STM32CubeMX should be able to provide me with the latest LWIP.

    BTW, I was using MX v6.11.1, the latest, and migrated the project from MX v6.11.0 to MX v6.11.1.

    Not sure why the migration seems to have failed without errors. Really MX v6.11.1 was used, not MX v6.11.0.

    S
    STea
    ST Employee
    July 8, 2024

    Hello @Jack3 ,

    This issue is resolved with the release of the new revision of CubeMX version 6.12.0
    Regards

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