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Visitor II
August 8, 2019
Question

Nucleo-STM32F429ZI Ethernet + LWIP (RAW API) - doesn't work.

  • August 8, 2019
  • 2 replies
  • 1157 views

I've got a project in which I have to communicate by Ethernet (TCP) Nucleo-STM32F429ZI with PC. STM32 will be sending the data from sensor periodically. I'm using STM32CubeIDE with built in CubeMX. I've connected the STM32 and the PC with a crossed cable. I configured it without RTOS, only using LwIP in RAW API mode with static IP addresses. I’m calling the MX_LWIP_Process() function in while loop.

My problem is that I can't receive ping response from STM32 and I’m getting the “Destination Host Unreachable�? message. I've tried every configuration and advice I found on forums and it didn't work. I've tried to adapt my project configuration to that from the example for my board (LwIP_HTTP_Server_Netconn_RTOS which works and response) but it didn't work too. 

As I'm debugging my project I can receive the ARP frame with request for IP address and I can see in debugger that the output frame is correct but as the whole payload is passed to "HAL_ETH_TransmitFrame" function, the output/response frame is gone, I can't see it in the Wireshark. I've checked the pinout configuration for the Ethernet peripheral and the configuration addresses. I really don't know what I’m missing. 

I've got auto-negotiation enabled in ETH CubeMX and I've change the PHY address from default 1 to 0 and PHY Link down inturrupt from 0xB to 0x10 according to datasheet (I hope it's correct).

Below I pasted my configuration for Ethernet PHY (LAN8742A):

/* LAN8742A_PHY_ADDRESS Address*/

#define LAN8742A_PHY_ADDRESS           0U

/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/

#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFFU)

/* PHY Configuration delay */

#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)

#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)

#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)

/* Section 3: Common PHY Registers */

#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */

#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */

#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */

#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */

#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */

#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */

#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */

#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */

#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */

#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */

#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */

#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */

#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */

#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */

#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */

/* Section 4: Extended PHY Registers */

#define PHY_SR                          ((uint16_t)0x1FU)    /*!< PHY status register Offset                      */

#define PHY_SPEED_STATUS                ((uint16_t)0x0004U)  /*!< PHY Speed mask                                 */

#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010U)  /*!< PHY Duplex mask                                 */

#define PHY_ISFR                        ((uint16_t)0x001DU)    /*!< PHY Interrupt Source Flag register Offset   */

#define PHY_ISFR_INT4                   ((uint16_t)0x0010U)  /*!< PHY Link down inturrupt       */ 

My whole project is in the attachment. If you need any additional information about the setup please ask. Thank you very much for any help.

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    2 replies

    Visitor II
    October 19, 2020

    Hi Nukat,

    Did ou solve your problem? I´ve just bought a nucleo-F429Zi board to implement a socket project. What do you think? can I use this board? Will it support ethernet communication?

    Thanks,

    Geraldo.

    Visitor II
    June 29, 2022

    your problem might be in platform setting section of LWIP