PLL: anybody using the internal PLLs as VCO for audio?

[LCE]

Hello,

I was just porting a F767 design to an H723-Nucleo, and found out that this H7 Nucleo is using its ST-Link's HSI as a clock source to the H723 at 8 MHz. With the usual terrible HSI quality, which showed itself in low quality SPDIF TX and PTP sync.

So I switched the ST-Link's clock to HSE output, which changed the frequency to 8.333 MHz, which again led me to using the FRACN registers for the first time to get some even clock numbers.

I also found that the FRACN values can be changed on the fly, which might let me save an external VCO (which until now I controlled with the 12bit DAC).

So, has anybody ever used the internal PLL's FRACN for syncing and sourcing audio stuff?

If yes, how was the quality (jitter while changing FRACN)?

[FBL]

Hello @Community member​,

For S/PDIF signal conversion, care must be taken while using electrical adapter to avoid jitter, and duty cycle degradation. You may refer to AN5073 section 2.1 for more details.

In order to get more information about peripherals dedicated to audio applications with STM32H723 products, subchapter 8.5.8 of RCC chapter in RM0468.

[LCE]

For now it looks quite good, though I need to build more boards to check synchronization.

In the H723, the SAIs / I2Ss get their clock from PLL2, and PLL2's FRACN is set by a PID controller, which is fed from the PTP_PPS signal via timer channel capture.

[LCE]

Update, using PLL / FRACN for syncing multiple boards via ethernet / PTP:

- jitter with sigma delta (audio) converters (TI's ADS127L01) is good concerning audio signal quality

- for exact, "sample-stable" sync (at 200 kHz) the FRACN solution is too coarse, I get much better and smoother results with external VCO (MEMS, surprised how good these are these days) controlled by internal DAC