possible inconsistency between the RM and the handling of DMA by HAL
ref. RM0440 Rev 9 vs STM32G4xx HAL v1.2.5.0 (en.stm32cubeg4-v1-6-1.zip)
DMA_CCRx.EN - Channel enable
This bit is set and cleared by software.
When a channel transfer error occurs, this bit is cleared by hardware.
DMA_CCRx.TCIE - Transfer complete interrupt enable
DMA_CCRx.HTIE - Half transfer interrupt enable
DMA_CCRx.TEIE - Transfer error interrupt enable
This bit is set and cleared by software.
It is not read-only when the channel is enabled (EN = 1).
It must not be written when the channel is enabled (EN = 1).
"it is not read-only" but "it must not be written when the channel is enabled"
unless RM is a cookbook, this is a must, not a suggestion.
This means that if DMA_CCRx.EN == 1, changing the IE bits along with EN = 0 in a single write must be avoided to prevent entering unpredictable states.
Can ST be exhaustive about changing IE bits along with EN in single writes of DMA_CCRx?
Function HAL_DMA_IRQHandler():
disregarding the RM, __HAL_DMA_DISABLE_IT() is called where the condition DMA_CCRx.EN == 1 is plausible,
in the sections Half Transfer Complete Interrupt management and Transfer Complete Interrupt management.
Function HAL_DMA_Abort():
__HAL_DMA_DISABLE_IT() is called before __HAL_DMA_DISABLE().