Reference manual doesn't show bitfield "SIOO" in OCTOSPI's CCR register

[DanPy]

Hello everyone,

I am writing my own "LL" for the OCTOSPI of the STM32H5 Series. (Because it seems there is only the HAL for it)

And I noticed that in the reference manual that the bitfield SIOO in the CCR register is written as "Reserved, must be kept at reset value", but is used by the HAL.

Bellow, taken from "XSPI_ConfigCmd"

 

/* Configure the CCR register with DQS and SIOO modes */
 *ccr_reg = (pCmd->DQSMode | pCmd->SIOOMode);

#define XSPI_CCR_SIOO_Pos (31U)
#define XSPI_CCR_SIOO_Msk (0x1UL << XSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
#define XSPI_CCR_SIOO XSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */

Reference manual is RM0481 Rev 3 from March 2025 and the HAL is the V1.5.0 from the 05 February 2025.

 

Is this a mistake in the RM? Can I use this SIOO bitfield?

 

Thank you in advance.

[KDJEM.1]

Hello @DanPy  and welcome to the community;

 

Thank you for bringing this issue to our attention.

I will check this internally and I will come back to you as soon as possible.

 

Thank you.

Kaouthar

[Tesla DeLorean]

Which H5 specifically. Seem to recall having to support a couple of models for the External Loaders

[DanPy]

I am writing my LL to support any H5, but right now I am working on the STM32H533RET6.

[KDJEM.1]

Hello @DanPy ;

 

I confirm that the SIOO bit isn't available on the OCTOSPI of STM32H562/63/73 and STM32H523/33 devices.

 

Thank you for your contribution in STCommunity.

Kaouthar