RMII problem STM32F7, receive OK, transmit not working

[Gossamer]

I am implementing ethernet on bare metal STM32F746-DISCO board. I configured rmii, set the PHY interface and "happily" receiving packaged on the DMA buffer. Problem is that sending doesnt work.

Before setting TX descriptor for first package, DMA_SR for TPS is = b110 (Suspended).

First package: TX descriptor OWN status is cleared, I set the buffer size and set the first/last flag in the status word of the descriptor and after that give control to DMA by setting OWN bit.

DMATDLAR is pointing to the TXDesc.

also DMACHTDR and DMACHTBAR looks OK.

then I set DMATPDR to 0x1 (it says set to any value) to trigger DMA check for new descriptor.

DMASR never get changed: TS, TBUS or TPS. Seems like its still waiting for something from cpu?

TX Descriptor never got returned to the CPU (DMA doesnt clear the OWN bit).

I checked example project LwIP for verification that the board is OK, and it works fine, so something in my code is not correct.

[waclawek.jan]

Maybe starting point could be reading out the ETH registers content (and maybe relevant GPIO, too, for good measure) and comparing them with the working case.

JW

[Gossamer]

I suppose MPU registers and SBC are the ones controlling the cache and memory barriers, so thats probably where I should focus next..

[Piranha]

Just a guess, but it seems that you have placed the DMA descriptors in a cached memory. For a development purposes just do not turn on the D-cache at all. Also can be related to this:

https://community.st.com/s/question/0D50X0000C4Nk4GSQS/bug-missing-compiler-and-cpu-memory-barriers

And anyway...

https://community.st.com/s/question/0D50X0000BOtfhnSQB/how-to-make-ethernet-and-lwip-working-on-stm32

[Gossamer]

Thanks. My descriptors were on the stack but still within the first bank. Now whats funny is that RX worked fine. I suppose its triggered in a different way. I moved the descriptors to second bank and now transmit works but its still very flaky.. I have to read bit more about D cache..