STM32F4 SPI with DMA, LL API: no interruption at the end of the transfer

[FWX]

Hello,
I am using a STM32F427 to read and write data to EEPROM Serial 256-Kb SPI
CAT25256. I use LL API, and DMA full-duplex over SPI. I manage myself the Chip Slect signal.
I can see with logic analyser that datas are sent and received to/from EEPROM correctly.
But I do not have interruption from DMA, neither input or outputstream.
I do not understand why.
The only way to detect the end of the transfer is to look at the BSY flag LL_SPI_IsActiveFlag_BSY(pSPI_Instance). Could-you help me to find where is the problem?
Thank you for help.
Best regards,
                                                        FWX.
I 

[Saket_Om]

Hello @FWX 

 

Could you enable the transfer complete interrupt on SPI and check if it is set after the data transfer?

[FWX]

Hi Omar,
Transfer complete interrupt is enable for both input and output streams in ddi_eeprom_init():

// Enable Transfer error interrupt
LL_DMA_EnableIT_TE(pDMA_SPI_Instance, InputStreamNumber);
// Enable Transfer complete interrupt
LL_DMA_EnableIT_TC(pDMA_SPI_Instance, InputStreamNumber);
// Enable Direct Mode error interrupt
LL_DMA_EnableIT_DME(pDMA_SPI_Instance, InputStreamNumber);

// Enable Transfer error interrupt
LL_DMA_EnableIT_TE(pDMA_SPI_Instance, OutputStreamNumber);
// Enable Transfer complete interrupt
LL_DMA_EnableIT_TC(pDMA_SPI_Instance, OutputStreamNumber);
// Enable Direct Mode error interrupt
LL_DMA_EnableIT_DME(pDMA_SPI_Instance, OutputStreamNumber);

NVIC is also well confgured in MX_DMA_init():

/* DMA2_Stream3_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),9, 0));
NVIC_EnableIRQ(DMA2_Stream3_IRQn);
/* DMA2_Stream4_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),9, 0));
NVIC_EnableIRQ(DMA2_Stream4_IRQn);

It is why I do not understand why I do not have interrupt.
Thank you for your answer.

                                   FWX.

[FWX]

Hi Omar,
Sorry, I answered the question wrong.
For output stream (4), when the output transfer is done, when BSY flag is cleared, the HISR register contains 0x30 (DMA_HISR_TCIF4|DMA_HISR_HTIF4): Transfer complete!So, I do not understand why the interrupt handler DMA2_Stream4_IRQHandler() is not called.
Best regards,

                                FWX.

[waclawek.jan]

You have to clear the flags causing the interrupts (i.e. DMA_LISR/HISR flags) in the ISR. Otherwise, the ISR gets invoked over and over.

JW

[FWX]

Hi Jan,
The problem is not that the interrupt handler is called over and over, but that the interrupt handler is never called.
Before activating DMA streams, interrupts are cleared:

/* Clear all interrupt flags at correct offset within the register */
WRITE_REG(pDMA_SPI_Instance->LIFCR, DMA_LIFCR_CHTIF3|DMA_LIFCR_CTCIF3|DMA_LIFCR_CTEIF3|DMA_LIFCR_CDMEIF3|DMA_LIFCR_CFEIF3);
WRITE_REG(pDMA_SPI_Instance->HIFCR, DMA_HIFCR_CHTIF4|DMA_HIFCR_CTCIF4|DMA_HIFCR_CTEIF4|DMA_HIFCR_CDMEIF4|DMA_HIFCR_CFEIF4);

Same in interrupt handler, but never called with priority greater or equal to 5 (because of FreeRTOS needed).
If priority of interruption are 0 or 1, interrupt handler are called. This is my problem.
Have you an idea?

Thank you for your help.

[waclawek.jan]

> Same in interrupt handler, 

>> WRITE_REG(pDMA_SPI_Instance->LIFCR, Status);

OK I overlooked that, sorry.

 

> The problem is not that the interrupt handler is called over and over, but that the interrupt handler is never called.

How do you know?

JW

 

[FWX]

Because I set an indicateur in the interrupt handler, and my main loop is waiting for this indicator to change.
I also put a breakpoint in the interrupt handlers, for both input and output stream, but never stopped.
But I can see the transfer complete flag set in interupt status register when I stopped the code.
See capture screen image attached.

[waclawek.jan]

Interesting.

I don't use FreeRTOS so can't help with this further, sorry.

JW

[FWX]

Ok. Thank you Jan.