stm32f429i PLL RCC configuration with registers for 48mhz HCLK

[YagciOnur]

Hello.Im tring to make an rcc configuration for my stm32f429i discovery board for 48mhz HCLK with ahb1 prescaler is 1.According to STM32CUBEMX ,pllm is 4,plln is 192,pllp is 8 for 8Mhz HSE.wHEN I DEBUG THE CODE,HCLK still showing 180Mhz and this never changes with different configurations.I have tried everything but no result.You have any idea?

#include "stm32f4xx.h"
#include "stm32f429i_discovery.h"
void rcc_config(void) {
RCC->CR=0x00000000; //resetting Control register
RCC->CR |= (1<<16); //HSEON enabled
while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) !=SET); //wait until flag rises
RCC->APB1ENR |= 1<<28;
PWR->CR |= 3<<14;
FLASH->ACR = (1<<8) | (1<<9)| (1<<10)| (5<<0);
RCC->CFGR &= ~(1<<4);
RCC->CR |= (1 << 19); // CSS On
RCC->PLLCFGR= 0x24003010; //Resetting PLL register
//This function must be used only when the main PLL is disabled.
RCC->CR |= (0<<24); //Disabling Main PLL
RCC->PLLCFGR |= (0<<5) | (0<<4) | (0<<3) | (1<<2) | (0<<1) | (0<<0);//pllm value is 4
RCC->PLLCFGR |= (0<<6) |(0<<7) | (0<<8) | (0<<9) | (0<<10) | (0<<11) | (1<<12) | (1<<13) | (0<<14);//plln is 192
RCC->PLLCFGR |= (1<<16) | (1<<17);//pllp is 8
RCC->PLLCFGR |= (1<<22); //PLL (PLLI2S) entry clock source is HSE
RCC->CR |= (0<<24); //Enabling Main PLL
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) !=SET);
RCC->CFGR |= (0<<0) | (1<<1);
while(!(RCC->CFGR & (2<<2)));
//After enabling the main PLL, the application software should wait on
//PLLRDY flag to be set indicating that PLL clock is stable and can
//be used as system clock source.


}
int main(void)
{
RCC_ClocksTypeDef rcc_clocks_struct;
rcc_config();


 STM_EVAL_LEDInit(LED3);
 STM_EVAL_LEDInit(LED4);

 STM_EVAL_LEDOn(LED3);
 STM_EVAL_LEDOn(LED4);

 while (1)
 {
 SystemCoreClockUpdate();
 RCC_GetClocksFreq(&rcc_clocks_struct);
 }
}


uint32_t sEE_TIMEOUT_UserCallback(void)
{
 while (1)
 {
 }
}

[TDK]

> RCC->PLLCFGR= 0x24003010; //Resetting PLL register
> ...
> RCC->PLLCFGR |= (0<<5) | (0<<4) | (0<<3) | (1<<2) | (0<<1) | (0<<0);//pllm value is 4
> RCC->PLLCFGR |= (0<<6) |(0<<7) | (0<<8) | (0<<9) | (0<<10) | (0<<11) | (1<<12) | (1<<13) | (0<<14);//plln is 192
> RCC->PLLCFGR |= (1<<16) | (1<<17);//pllp is 8
> RCC->PLLCFGR |= (1<<22); //PLL (PLLI2S) entry clock source is HSE

 

The register is not 0 to start with so you need to clear relevant bits in addition to setting them.

 

Write to PLLCFGR only once, with the configuration you want, rather than piecewise modifying it, which can lead to invalid settings. It's not a memory address, it's a configuration register.

 

Debug the code and examine the register values to see this clearly and ensure you've set the settings you think you did.

[YagciOnur]

I didnt understand clearing part.Didint i clean the bits by resetting the register with the reset value in the datasheet.

[TDK]

No, not really. Did you set it to 0? Because otherwise you're not clearing all bits.

This is very basic C stuff. If you're doing register-level access, perhaps look at a tutorial on how to manipulate bits.

[waclawek.jan]

RCC->CR |= (0<<24); //Enabling Main PLL

You are ORing with zero, this does nothing.

JW

[TDK]

This code seems artificially generated. Looks like it works at first glance, but under the hood is issue after issue.

[AScha.3]

Maybe : ask Ai to think, before write... 

[YagciOnur]

i didnt use ai while writing this,why did you think like that???