STM32F7 ethernet PTP PPS to timer 2

[LCE]

Hello,

I just got lwIP with PTPd on 2 Nucleo-144 with STM32F767ZI working.

Thanks to all the open source people out there!

PPS output is also working, I use these signals to check sync quality on a scope.

PPS from ETH goes to TIM2 via ITR1 input to TRGO to GPIOB pin 5.

So far so good...

Now I would like to use that PPS signal internally, but I don't get it to work within timer 2.

Neither as a counter reset signal, nor as a clock source for timer 2.

First I started using the HAL stuff, then I set all the registers (CR1, SMCR, DIER and more) "manually" - nothing!

Is there anything they forgot to mention in the datasheet / ref manual?

Right now it seems to me that this PPS signal is only routed to the TRGO output and can NOT be used otherwise by timer 2.

Anybody an ideas?

Thanks in advance!

[Tesla DeLorean]

Configured via bits 10,11 in TIM2->OR

OR.ITR1_RMP = 01b ETH_PTP

SMCR.TS = 001b ITR1

SMCR.SMS = 0111b EXT CLK MODE1

PSC = 0

ARR = 0xFFFFFFFF

[LCE]

Hello TDL,

thanks for your reply.

Please see my post below, thanks!

[LCE]

Hello TDL,

thanks for your reply.

Unfortunately this is one of the many settings I already tried.

The UART output shows me that I set the registers (TIM2->) this way, which should be equal to what you wrote above:

CNT = 0x00000000 = 0 ==>> so nothing happened at all

CR1 = 0x0081 ==>> enabled and ARR buffered (doesn't matter)

CR2 = 0x0000

SMCR = 0x00000017 ==>> ITR1 as input & clock (I tried several other settings, including reset)

DIER = 0x0041 ==>> interrupts: update and trigger in (I tried several other settings)

SR  = 0x0000 ==>> nothing happened

PSC = 0x0000 = 0

ARR = 0xFFFFFFFF = 4294967295

OR  = 0x0400 ==>> remap, doesn't matter

CNT dif = 0 in 5136 ticks ==>> checked counter with SysTick

Additionally, "TIM2_IRQn" is enabled, I also checked the NVIC->ISER[TIM2_IRQn>>5] register directly.

From what I have tried until now, I found out the following (checked on 2 Nucleo boards):

• the OR register or any remap commands for ETH_PPS to GPIO are not necessary, timer 2 doesn't even need to be enabled, ONLY the GPIO needs to be configured with the alternate function!
• it looks like there's a hardware switch in the timer's trigger section, which routes ITR1 = PPS to TRGO, and disables all other of the timer's trigger functions

Shoot, that bugs me... ;)

[LCE]

Played with it some more.

At the end of SMCR register description in the F7 ref manual:

Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2

signals must be enabled prior to receive events from the master timer, and the clock

frequency (prescaler) must not be changed on-the-fly while triggers are received from

the master timer.

So... that helps, but only when using the external trigger hardware pin as a clock input.

I tried that with wiring PB5 (PPS out) to PE0 (timer 4) and PA5 (timer 2), that works,

but only if timer configuration (SMCR = 0x0077 or SMCR = 0x4000) is set before GPIO as PPS

is activated.

Again, that verifies the above mentioned behavior, that the PPS output is set only by the

GPIO alternate setting, nothing else.

And again, no way to use the PPS signal as an internal trigger signal.

I tried it as ITR1 for timer 2 or timer 4, that does not work, no matter how TIM2->OR is set.

Very frustrating!

Anyone from ST can tell me more?

[LCE]

How an I get more info about the PPS / timer trigger routing from ST?

Anybody?

Would be nice to know if I screwed up or if the F7 ref manual is not "complete".

[Piranha]

Are the RCC_AHB1ENR_ETHMACPTPEN enabled?

Does your code take into account ES0334 section 2.17.5?

Anyway I will test this issue on my F7 based platform and report back here.

[LCE]

Hi Piranha,

thanks for your reply!

Bit RCC_AHB1ENR_ETHMACPTPEN was NOT enabled.

Interestingly everything concerning PTP worked (except for the timer stuff), setting this bit hasn't changed anything.

I have timers 2 and 4 running, I can switch their trigger source via UART command, using

SMCR = 0x17 (ITR1 as clock), or

SMCR = 0x77 / 0x4000 (ext as clock)

It's still NOT working with ITR1 as timer clock source.

PS: Although that bit's name is kinda self-explaining I didn't find a description or any reference to that anywhere.

Re: Does your code take into account ES0334 section 2.17.5?

Yes it does, I have checked the relevant registers.

The PTP and ethernet stuff (until now only http server) run smoothly, PTP/PPS output also works.

Only using PPS as internal trigger as counter clock does not work.

[LCE]

Hello @Piranha​ ,

have you tested the PPS trigger behavior?

I'm still not getting it internally to Timer 2, no matter what the SMCR or OR settings are.

[LCE]

 @PatrickF​ or some other employee, could you please have a look at this?

Summary of the problem:

STM32F767, ethernet PPS signal never appears internally at TIM2, although it should be available as ETH_PTP = ITR1, according to reference manual (RM0410, page 1012, Table 177. TIMx internal trigger connection)

ALL register settings were tried and checked, see above.

[Piranha]

Hello!

I tested and figured this out. There are two separate timing signals from the PTP module:

• PTP trigger. The target time is set in a ETH_PTPTTHR and ETH_PTPTTLR registers. This one is connected to TIM2 ITR1.
• PPS output. The frequency is set in a ETH_PTPPPSCR_PPSFREQ bit field. This one is connected to ETH_PPS_OUT.

The whole misunderstanding is because of a documentation error.

RM0410 Rev 4 page 1806, paragraph "PTP trigger internal connection with TIM2" is true:

This PTP trigger signal is connected to the TIM2 ITR1 input selectable by software. The connection is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR). Figure 565 shows the connection.

RM0410 Rev 4 page 1807, paragraph "PTP pulse-per-second output signal" is false:

The PPS output is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR).

An interesting fact is that F2 series (RM0033 Rev 9 page 880) and F4 series (RM0090 Rev 19 page 1163) have a correct PPS output description:

The PPS output is enabled through a GPIO alternate function. (GPIO_AFR register).

Obviously the F7 reference manual is based on F4/F2 manuals. I just wonder why someone "corrected" that description to the wrong one.

@Imen DAHMEN​

[Piranha]

Noticed some other errors in RM0410 Rev 4.

Page 1866, ETH_PTPTTHR description:

The Target time high register, along with Target time low register, is used to schedule an interrupt event (TSARU bit in ETH_PTPTSCR) when the system time exceeds the value programmed in these registers.

TSARU bit has nothing to do with this. The description means TSITE bit.

Also there are two places, where the TSARU bit is named wrongly as TTSARU - pages 1860 and 1884. The Ctrl+F will show exactly where...

[Imen.D]

Hello @Piranha​ ,

Thank you for bringing this post to my attention.

I really appreciate your collaboration with @Community member​, and your answer has been very helpful.

I escalated the internal ticket (ID 118901) to involved team to correct the errors.

(PS: The internal ticket ID 118901 is an internal tracking number and is not accessible or usable by customers).

Thanks

Imen