Question
STM32F723 I2C bootloader : No-Stretch Erase command leads to long clock stretching anyway. How to deal with it?
Several questions:
- The I2C bootloader answers version 1.2 which is not documented in AN4221 even though it was recently updated in June 2021. Is it planned to publish this information soon?
- I am sending a "No-stretch Erase" command via the following operations:
- I2C write to 0x4D : 0x45 ACK 0xBA ACK.
- I2C Read to 0x4D : 0x79 nACK.
- I2C Write to 0x4D : 0xFF ACK 0xFF ACK 0x00 ACK.
- Then I try to issue a Read to 0x4D (to get the ACK/nACK/BUSY status) and the STM32 does clock stretching (holding clk down) at the ACK/nACK bit for 7 very long seconds. Is it normal that during the process of a "No Stretch" command, I get a clock stretch? How is the erase supposed to work?
- Since polling by issuing I2C Reads seems to fail, then I tried to add a sleep(10) (10 seconds) before issuing the I2C read for the ACK/nACK/BUSY. On the I2C lines I can see indeed a big 10 seconds gap after the 0xFF ACK 0xFF ACK 0x00 ACK. During the GAP bus is idle (SCL == 1, SDA == 1). Then when I issue the Read 0x4D, the read itself is nACKed, as if the I2C device 0x4D (the bootloader) was gone.
- I also tried with a smaller sleep(1) (1 second), it gives the same result as when there is no sleep at all. Meaning that upon issuing the Read to get the ACK/nACK/BUSY msg, when it comes to the ACK bit of the I2C frame the clock gets stretched for 6 seconds.
You can find details on this issue I am having, including I2C wave dump screenshots on the following thread: https://sourceforge.net/p/stm32flash/tickets/131/
Thank you for your help.
Best regards,
Yann