STM32F723 USB-HS DMA problem with EP0

[Mehran Memarnejad]

Hello,

I am trying to use USB-HS DMA in my program... It works good with other endpoints except EP0

For EP0, the enumeration phase is done successfully, But when I start sending my USB class specific messages one after the other continuously on EP0, after some successful transmissions, it suddenly gets stuck and EP0 Nack status is set ... I also check that DMA address be 4byte-align

Note that there is no problem when DMA is disabled

What could be the probable mistake?

Thanks in advnace

[Ons KOOLI]

Hi Mehran,

Can you please share your .ioc file ?

Best Regards,

Ons.

[Mehran Memarnejad]

Hello,

The .ioc file is like a USB CDC example created by CubeMX plus some other peripherals like uart, spi and etc enabled

I guess it is not related to other peripherals and its about the USB itself ... As I said, there is no problem when DMA is disabled OR DMA is enabled but requests are sent one by one after a short delay (1 nano second with libusb) in between... The problem arises when DMA is enabled AND Data are sent continously without delay in between ... This problem is just for EP0, other EPs work well ... I should also mention that it is USB HS

I also made "uint32_t  Setup[12] __attribute__ ((aligned (4))); " in PCD_HandleTypeDef 4byte align to be USB DMA compatible which is used as buffer for setup packets ... But that does not fix the problem

Any idea about what the problem could be?

Best Regards

[Ons KOOLI]

Hi Mehran,

If I am well understanding, you want to use USB with DMA which means that you enabled:

 hpcd_USB_OTG_HS.Init.dma_enable = ENABLE;

Can you please specify which region of RAM are you using for your project?

If it is DTCM, ITCM, AXI SRAM, or ...?

Best Regards,

Ons.

[Mehran Memarnejad]

Hello,

yes, I have enabled DMA as you said

This is what comes in linker script to locate sections for data:

/* Initialized data sections goes into RAM, load LMA copy after code */
 .data : 
 {
 . = ALIGN(4);
 _sdata = .; /* create a global symbol at data start */
 *(.data) /* .data sections */
 *(.data*) /* .data* sections */
 
 . = ALIGN(4);
 _edata = .; /* define a global symbol at data end */
 } >RAM AT> FLASH
 
 
 /* Uninitialized data section */
 . = ALIGN(4);
 .bss :
 {
 /* This is used by the startup in order to initialize the .bss secion */
 _sbss = .; /* define a global symbol at bss start */
 __bss_start__ = _sbss;
 *(.bss)
 *(.bss*)
 *(COMMON)
 
 . = ALIGN(4);
 _ebss = .; /* define a global symbol at bss end */
 __bss_end__ = _ebss;
 } >RAM
 
 /* User_heap_stack section, used to check that there is enough RAM left */
 ._user_heap_stack :
 {
 . = ALIGN(8);
 PROVIDE ( end = . );
 PROVIDE ( _end = . );
 . = . + _Min_Heap_Size;
 . = . + _Min_Stack_Size;
 . = ALIGN(8);
 } >RAM

I guess it's not about the location of data.. As I said in USB HS:

1- All endpoints except EP0 work well when DMA enabled, so it shows that memory location may not be the problem as I made "uint32_t  Setup[12] __attribute__ ((aligned (4)));" to make sure that space allocated for setup packets be also 4byte align

2- All endpoints including EP0 work well when DMA disabled, so it shows that the problem might be something with DMA

The strange thing is that EP0 works well when I send packets with some delay in between (so the memory location may not be the source of problem) and it only stuck when packets are sent continuously one after the other without delay in between

I found something in Reference Manual but I did not understand it... That might also be related to my problem... I don't know, I just guess...

(stm32f72xxx reference manual, Rev 3, page 1278):

"STPKTRX: Setup packet received.

Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used."

"B2BSTUP: Back-to-back SETUP packets received for USB OTG HS Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint"

Thanks in advance,

Best Regards

[Ons KOOLI]

Hi Mehran,

I will raise the issue internally and provide you with solution as soon as possible.

Best Regards,

Ons.

[Mehran Memarnejad]

Hello,

Any idea?

[Ons KOOLI]

Hi Mehran,

Could you please enable B2B interrupt to confirm that a back to back setup is received by the IP.

Best Regards,

Ons.

[Mehran Memarnejad]

Hi,

I Enabled B2B interrupt in DOEPMSK register, but the b2b interrupt does not occur

Revise: As I inspected, the same problem exists when DMA is disabled, But the number of errors are less

More specifically, the error returned by libusb in Linux is LIBUSB_ERROR_PIPE

I guess there are some notes in using EP0 with DMA in USB HS ... I guess so, because there is some information in reference manual about this. For example reference manual says:

STPKTRX: Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS,

this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet

per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the

corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS

puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token

after the SETUP packet for that particular endpoint. The application must then re-enable the

endpoint to receive any OUT data for the control transfer and reprogram the buffer start

address. Because of the above behavior, OTG_HS can receive any number of back to back

setup packets and one buffer for every setup packet is used

Question: Is there any sample code which uses EP0 in USB HS when DMA is enabled? It can help me alot

Thanks in advance for your help

[James Murray]

I might be mistaken here, but you are using DMA for IN actions, the "back to back" setting refers to OUT actions.

James

[Mehran Memarnejad]

Hi,

I guess DMA is used for both IN and OUT actions. Anyway, I was testing B2B for OUT actions

[Mehran Memarnejad]

The problem was in USBD_LL_DataOutStage and USBD_LL_DataInStage that was fixed by removing these snippets from code:

In function USBD_LL_DataOutStage:

#if 0

     if (pdev->ep0_state == USBD_EP0_STATUS_OUT)

     {

       /*

        * STATUS PHASE completed, update ep0_state to idle

        */

       pdev->ep0_state = USBD_EP0_IDLE;

       USBD_LL_StallEP(pdev, 0U);

     }

#endif

In function USBD_LL_DataInStage:

#if 0

     if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||

         (pdev->ep0_state == USBD_EP0_IDLE))

     {

       USBD_LL_StallEP(pdev, 0x80U);

     }

#endif