STM32F767 : No Ethernet when APB2CLKDivider = RCC_HCLK_DIV8 or greater

[Joerg Wagner]

My SysClock is 200 MHz, AHB Prescaler=1.

I want to slow down some timer to filter glitches from external input.

But when APB2 peripheral clock is set lower than 50 MHz

the Ethernet DMA does not send any data: no ARP, UDP or TCP.

Even when ABP2 timer clock is set to 200 MHz to give it a try.

Why does APB2 peripheral clock takes advantage of Ethernet traffic?

I cannot find any dependencies on page 19 in the datasheet.

Thank you.

[PHolt.1]

The suggested fix works perfectly. ETH now running with DIV16 on PCLK2. Thank you!

https://peter-ftp.co.uk/screenshots/20210616453310512.jpg

[Piranha]

Hi, guys!

Recently @PHolt.1​ informed me about the following topic:

https://www.eevblog.com/forum/microcontrollers/stm32f417-any-reason-why-a-min-pclk2-speed-is-required-for-ethernet-to-work/

Reading the details, for testing purposes I modified my STM32F7 code to effectively the same as presented by @Adam BERLINGER​. Commenting out the dummy read, I got it failing at APB2 dividers of 8 and 16 with caches ON and only 16 with caches OFF. Adding a dummy read fixes all cases. Therefore now I can confirm both - the issue and the fix.

The reason my actual code is not failing is because I'm setting SYSCFG_PMC_MII_RMII_SEL bit early in board initialization and configuring ETH peripheral significantly later.

Thanks to @PHolt.1​ for digging this! I've added this topic to my list of Ethernet issues.