[STM32F767] Shift occurs when reading NAND memory data.

[togsin]

Dear all

nand memory device is MT29F4G. I attacing datasheet

first nand memory setting.

===========================================================

 hnand1.Instance = FMC_NAND_DEVICE;

 /* hnand1.Init */

 hnand1.Init.NandBank = FMC_NAND_BANK3;

 hnand1.Init.Waitfeature = FMC_NAND_WAIT_FEATURE_ENABLE;

 hnand1.Init.MemoryDataWidth = FMC_NAND_MEM_BUS_WIDTH_8;

 hnand1.Init.EccComputation = FMC_NAND_ECC_ENABLE;

 hnand1.Init.ECCPageSize = FMC_NAND_ECC_PAGE_SIZE_2048BYTE;

 hnand1.Init.TCLRSetupTime = 0;

 hnand1.Init.TARSetupTime = 0;

 /* hnand1.Config */

 hnand1.Config.PageSize = 2048;

 hnand1.Config.SpareAreaSize = 64;

 hnand1.Config.BlockSize = 64;

 hnand1.Config.BlockNbr = 2048;

 hnand1.Config.PlaneNbr = 2;

 hnand1.Config.PlaneSize = 2048;

 hnand1.Config.ExtraCommandEnable = DISABLE;

 /* ComSpaceTiming */

 ComSpaceTiming.SetupTime = 5;

 ComSpaceTiming.WaitSetupTime = 5;

 ComSpaceTiming.HoldSetupTime = 6;

 ComSpaceTiming.HiZSetupTime = 0;

 /* AttSpaceTiming */

 AttSpaceTiming.SetupTime = 5;

 AttSpaceTiming.WaitSetupTime = 5;

 AttSpaceTiming.HoldSetupTime = 6;

 AttSpaceTiming.HiZSetupTime = 0;

============================================================

when I read NAND nomal:

When I read Nand , data is shift

​

HAL_NAND_Read_Page_8b source :  

=====================================================================

   {

    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;

    __DSB();

    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;

    __DSB();

    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = Third_Address;//ADDR_1ST_CYCLE(nandAddress);

    __DSB();

    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = Fourth_Address;//ADDR_2ND_CYCLE(nandAddress);

    __DSB();

    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = Fifth_Address;//ADDR_3RD_CYCLE(nandAddress);

    __DSB();

   }

  }

  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;

  __DSB();

for(; index < size; index++)

  {

   *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;

}

=========================================================================

when I test on ST32F407 , it is working well.

But when I test on ST32F767 , data is shift.

Let me know why this is happening.

Thanks.

[waclawek.jan]

I don't attempt to understand the problem, but try to set the FMC area where the NAND is located as Device in MPU.

https://community.st.com/s/question/0D50X0000B42x2iSQA/stm32h743iit6-fmc-ne-producing-multiple-clocks

JW

[Tesla DeLorean]

The NAND reads like a FIFO, so will be sensitive to access cycles.

Don't view the memory in a debugger window.​

​Configure the MPU to not cached or buffer the memory area.

Suggest also moving efficiently as words rather than bytes.​

For support work with your local ST FAE​

[waclawek.jan]

Clive,

> Configure the MPU to not cached

I think it's not enough and it ought to be set as Device, to prevent read restarts (Device precludes automatically caching).

> buffer the memory area.

Can you please elaborate?

Thanks,

Jan

[Tesla DeLorean]

Relates to completion, you shouldn't need the fencing instructions if the memory space is described correctly, and it stops the writes being deferred.

To quote an ARM engineer

"bufferable write to a peripheral register is faster than non-bufferable write (if non-bufferable, the processor needs to wait for the write to complete before next instruction can execute)."

Trying to avoid Write Buffers, and Write-Back or Write-Thru behaviours.

I'd probably use a volatile cast in the memory copy used by the OP

The use of LDM might also have undesirable restart behaviour on FIFO memory.