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MBitt.2
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October 29, 2021
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STM32G0B0 and STM32G0B1 I2C Bootloader issue

  • October 29, 2021
  • 1 reply
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When working on the I2C bootloader embedded in the System Memory of the STM32G0B0CE (v13.0) and STM32G0B1RE (v9.2) MCUs, we noticed a strange behavior.

The Write Memory (0x31) and No-Stretch Write Memory (0x32) commands of the bootloader does not seem to work with addresses that are not at least 8-byte aligned. Commands issued on 4-byte aligned addresses are acknowledged by the bootloader (the ACK byte (0x79) is received upon the last I2C read of the command), but the data is never written to

memory. The size of the operation does not seem to change this behavior. For example, the bootloader acknowledges a Write Memory command on 0x08000004 but never actually writes it into flash, even though it has been previously erased. The Read Memory command (0x11) on that address returns 0xFF bytes which suggest that the flash has not been programmed.

On the other hand, if we try to perform a write operation on 0x08000000 using a 16 byte payload, everything works as it should (and as a consequence, the address 0x08000004 is also written).

Write memory commands on addresses that are not 4-byte or 8-byte aligned (0x08000002 for example) do not work: the last I2C read of the command fails because the bootloader NAK the I2C read. We are unable to obtain an ACK (0x79), NAK (0x1F) or Busy (0x76) byte for such commands.

On Linux, the stm32flash (https://sourceforge.net/p/stm32flash/code/ci/master/tree/) can reproduce this issue with the following command line:

$ stm32flash /dev/i2c-X -w /path/to/fw.bin -v -F 254:254

With this command, the firmware is written 0xFC bytes at a time, which means that half of the write operations silently fails because half of them are not on 8-byte aligned addresses.

Are there any constraints on the addresses that are passed to the Write Memory commands, or is this a bug in the bootloader ?

    This topic has been closed for replies.
    Best answer by Antoine Odonne

    Hello,

    By construction, the G0 Flash can only be programmed by double word as stated in RM:

    "The Flash memory is programmed 72 bits (64-bit data plus 8-bit ECC) at a time."

    More precisely it refers to alignment of 64 bits indeed <= 8 byte aligned.

    The I2C bootloader protocol does not implement an emulation for smaller buffer support or unaligned _ bytes data most likely. Indeed you would anyway have to write your section at address xxxxx0 to xxxxxx4 with something in order to write xxxxx4 to xxxxxx8 too. programming 0xFFFF would not be erased state anymore also, due to the ECC code, different for erased data and for programmed "..FFF.."

    I will consolidate this with BL development team but i suppose it might explain your issue.

    Memory line size are not product dependent and may vary from series to series meanwhile I2C BL protocol not.

    Hope it helps,

    Best regards,

    Antoine

    1 reply

    A
    Antoine OdonneAnswer
    ST Employee
    October 29, 2021

    Hello,

    By construction, the G0 Flash can only be programmed by double word as stated in RM:

    "The Flash memory is programmed 72 bits (64-bit data plus 8-bit ECC) at a time."

    More precisely it refers to alignment of 64 bits indeed <= 8 byte aligned.

    The I2C bootloader protocol does not implement an emulation for smaller buffer support or unaligned _ bytes data most likely. Indeed you would anyway have to write your section at address xxxxx0 to xxxxxx4 with something in order to write xxxxx4 to xxxxxx8 too. programming 0xFFFF would not be erased state anymore also, due to the ECC code, different for erased data and for programmed "..FFF.."

    I will consolidate this with BL development team but i suppose it might explain your issue.

    Memory line size are not product dependent and may vary from series to series meanwhile I2C BL protocol not.

    Hope it helps,

    Best regards,

    Antoine

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