STM32G4 Errata 2.7.9 ADC trigger sequencing

[mitk]

ES0430 - Rev 8 - March 2023

2.7.9 An ADC instance may impact the accuracy of another ADC instance at specific conditions

Has anyone implemented this item listed in the Errata sheet for STM32G4 series for ADC section? It asks for:
Ensure that conversions by different ADC instances do not occur concurrently. This can be achieved
through trigger sequencing by the application software.

 

STM32G4 Errata sheet 

[Imen.D]

Hello @mitk and welcome to the Community :)

For which application needs? Please provide more details on your use case.

For example, use ADCs in non-continuous mode, you can use PWM signal: rise edge will start ADC1 and fall edge will start ADC2. 

With pulse width equal to the required delay between both ADCs. PWM high time must be higher than ADC1 total conversion time.  PWM low time must be higher than ADC2 conversion time.

Imen

[mitk]

Hi @Imen.D,

I am using 4 ADCs and a total of 11 channels scattered over all 4 ADCs. Currently, we use free-running DMA transfer P2M for all of them and the application is reading the data from the specified buffer.

In the Errata ES0430, 2.7.9; it is recommended to run it sequentially, so looking for a solution if anyone has similar to this implemented.

Mithun

[mitk]

Hi @Imen.D 

any updates?

 

regards

Mithun