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Visitor II
June 15, 2021
Solved

STM32G473 svd file defect

  • June 15, 2021
  • 8 replies
  • 2802 views

STM32G473 svd file (used in STCubeIDE in SFR view) shows FDCAN message RAM as if it was another instance of FDCAN peripheral

    This topic has been closed for replies.
    Best answer by Amel NASRI

    Hi @Community member​ ,

    You find attached an updated version of STM32G473 SVD file. You can use it, waiting for its integration on the STM32CubeIDE and other IDEs.

    Don't hesitate to come back with other feedback you may have.

    -Amel

    8 replies

    Graduate II
    June 15, 2021

    @Imen DAHMEN​  @Amel NASRI​ 

    TMark.14Author
    Visitor II
    June 15, 2021

    Also FLASH OPTR register is missing DBANK bit, or, actually it looks very different from Reference Manual.

    Technical Moderator
    June 16, 2021

    Hi,

    Thanks @Community member​  for reporting this issue & @Community member​  for bringing it to our attention.

    I highlighted it to the team maintaining SVD files who will take care to provide a fixed version.

    Internal ticket number: 109123.

    -Amel

    TMark.14Author
    Visitor II
    June 16, 2021

    I had to keep looking into FLASH peripheral and I found that CR register is missing some of the bits also (e.g BKER).

    This particular project is in Atollic True Studio but I use svd file from ST Cube IDE version is 1.6.0

    C:\ST\STM32CubeIDE_1.6.0\STM32CubeIDE\plugins\com.st.stm32cube.ide.mcu.productdb.debug_1.6.0.202102151443\resources\cmsis\STMicroelectronics_CMSIS_SVD\STM32G473xx.svd

    Also I compared the file with what comes from Keil uvision STM pack and it is identical file.

    Reference Manual RM0440 Rev 6

    TMark.14Author
    Visitor II
    June 16, 2021

    Actually I was wrong, the bits are not missing, the description of the registers seems to be for another MCU series.

    Technical Moderator
    June 16, 2021

    Hi @Community member​ ,

    You speak about FLASH_CR register, right? Because that is true: DBANK bit description is missing in STM32G473xx.svd which is a category 3 device.

    -Amel

    TMark.14Author
    Visitor II
    June 16, 2021

    Yes, I meant FLASH_CR register, you are right STM32G473 is a category 3 device, and SVD file for it might be missing bits that are related to DBANK feature overall.

    TMark.14Author
    Visitor II
    June 21, 2021

    What's up?

    Is that really a defect in svd file or not or you are still investigating?

    You provided an internal ticket number, does that mean I can look at it?

    Technical Moderator
    June 25, 2021

    Hi @Community member​ ,

    Internal ticket goes to the team responsible of SVD files maintenance. Unfortunately you don't have access to it.

    But I'll keep you informed as soon as I get an update on this regard or even the fixed file. The ticket number makes it easy for us to look for status on the internal base.

    -Amel

    Technical Moderator
    July 12, 2021

    Hi @Community member​ ,

    You find attached an updated version of STM32G473 SVD file. You can use it, waiting for its integration on the STM32CubeIDE and other IDEs.

    Don't hesitate to come back with other feedback you may have.

    -Amel

    TMark.14Author
    Visitor II
    July 15, 2021

    Are FDCAN bitfields defined backwards?

    If I look at FDCAN register they start LSB on the top and MSB on the bottom. Then I look at one of the timers bit definitions and they are defined MSB at the top and LSSB on the bottom.

    TMark.14Author
    Visitor II
    July 15, 2021

    Also I should have added that in Reference Manual bits are (I think always) defined starting with MSB on the top, and LSB on the bottom.