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liszt
Visitor II
September 29, 2024
Solved

STM32H562RG LSE crystal oscillation issue.

  • September 29, 2024
  • 2 replies
  • 1063 views

I am using a STM32H562RG and my project involves timing, for which I am using an external LSE crystal. I know that the STM32H562RG can adjust the LSE drive level. I used STM32CubeMX to generate the code. I noticed this code comment.

/** Configure LSE drive capability
* WARNING: Only applicable if LSE is disabled.
*/

I don't understand. What should I do? When I used STM32L431 before, there was no such code comment.
Because when I set the level to HIGH, the LSE crystal of the STM32H562RG still does not oscillate. I don't know what I am doing wrong.

 

This post has been translated from Chinese to comply with the ST Community guidelines.

    This topic has been closed for replies.
    Best answer by KDJEM.1

    Hello @liszt ,

     

    This warring is displayed because in STM32H5 the driving capability must be set before enabling the LSE oscillator as mentioned in RM0481 that the.

    KDJEM1_0-1728392750349.png

    For that, LSEDRV bit used to select the driving capability of the LSE can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)

    KDJEM1_3-1728392989683.png

    So, this warning means that you should take care, the LSE must be disabled before select the driving capability.

    This condition is not available for STM32L431 as shown in RM0394

    KDJEM1_2-1728392957318.png

    >the LSE crystal of the STM32H562RG still does not oscillate. I don't know what I am doing wrong.

    Are you update its code generation on LSE drive level without powering down/up the HW (ie. disconnect/reconnect the board)? If yes, the backup domain which control the LSE is not reset and LSE remains ON between the two tries. Please update your code as shown in below and let me know if the issue is solved or not?

     

    HAL_PWR_EnableBkUpAccess();
 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);

     

    Thank you.

    Kaouthar

    2 replies

    L
    lisztAuthor
    Visitor II
    September 30, 2024

    500b844c8d654cc818ee590db5e6b72.jpgfbeecc812cfcdd86c57fb0c7d220b01.jpgI'm sorry, I sent it in Chinese by mistake. It might have been due to automatic translation on the web page. I will add two more pictures.

    K
    KDJEM.1Answer
    Technical Moderator
    October 8, 2024

    Hello @liszt ,

     

    This warring is displayed because in STM32H5 the driving capability must be set before enabling the LSE oscillator as mentioned in RM0481 that the.

    KDJEM1_0-1728392750349.png

    For that, LSEDRV bit used to select the driving capability of the LSE can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)

    KDJEM1_3-1728392989683.png

    So, this warning means that you should take care, the LSE must be disabled before select the driving capability.

    This condition is not available for STM32L431 as shown in RM0394

    KDJEM1_2-1728392957318.png

    >the LSE crystal of the STM32H562RG still does not oscillate. I don't know what I am doing wrong.

    Are you update its code generation on LSE drive level without powering down/up the HW (ie. disconnect/reconnect the board)? If yes, the backup domain which control the LSE is not reset and LSE remains ON between the two tries. Please update your code as shown in below and let me know if the issue is solved or not?

     

    HAL_PWR_EnableBkUpAccess();
 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);

     

    Thank you.

    Kaouthar

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