STM32H7 dual core: data sharing between cores (CM7 and CM4)

[Srinath_03]

Hi, in STM32H7 dual core, i have an example of data sharing between the core using ring buffer method, here when caches are enabled, the data sharing is not happening what will be the reason. when caches enabling lines are disabled data sharing is happening. 

ring buffer is placed in D3 SRAM 

 

 

 

regards.

Srinath

[mfgkw]

The cache caches memory access for each core. So it is known to be incoherent when accessing memory through two caches from two cores.

You can start reading here for example: https://community.st.com/t5/stm32-mcus-products/how-we-can-communicate-between-two-cores/td-p/222905 or https://community.st.com/t5/stm32-mcus-products/core-comunication-using-stm32h7/m-p/163717

[TDK]

 

With cache enabled, you will need to clean the cache after every write and invalidate it before every read. It would be better to set the region as non-cacheable using the MPU so you can avoid this.

[mƎALLEm]

Hello,

That's an expected behavior due to a cache incoherency behavior. While you suppose the CM7 is writing to D3_SRAM, it's is for instance writing to the cache and the data doesn't hit the memory CM4 is not seeing that data updated. So you need to apply the cache maintenance or disable the cachability to that shared memory region using the MPU.

You can refer to the AN4839 "Level 1 cache on STM32F7 Series and STM32H7 Series" especially the example provided in 3.2 Example for cache maintenance and data coherency. The example is using DMA which is a bus master: same case as CM4.