STM32H7: ETH & SAI DMA can access memory-mapped Octo/Quad SPI RAM?

[LCE]

Heyho,

I am really a little confused by ST's documentation vs. comments here and elsewhere, so in hope of finding someone with first hand experience:

Which STM32H7 can use external memory-mapped Octo-/Quad-SPI RAM via DMA with the Ethernet and SAIs ?

My "candidates": H723, H725, H733, H735

H743 & friends has no Q/O-SPI SRAM interface, and if possible I want to avoid the 2-core H7s.

I need this data flow:

SAI (RX) -> DMA -> ext. Q/O-SPI-SRAM -> DMA -> ETH

Thanks in advance!

[Pavel A.]

H743 does work with QSPI SRAM, for example this.

The board is no longer with me so cannot test the DMA.

ETH likely cannot access it. Consider that ETH has its own master DMA, it does not use the DMA controllers of the STM32. See the bus matrix pictures in the RM.

[LCE]

@Pavel A.​  thanks for your input!

I think the H743 does not support memory-mapped QSPI SRAM.

Just found it in the RM0433, pg. 895:

"Only read operations are allowed to the external Flash memory in this mode."

And I only read "Flash" all the time... ;)

Concerning DMA / memory access:

What about the Dx-to-Dy AHB bridges, these cannot be used by the DMA controllers?

If these are working, are they slowing things down ?

The thing is that the RMs show that access from SAI (DMA2) and ETH DMA is possible, but from users I read differently.

Here's the interconnect matrix for the H723+:

Here for the H743:

 

[LCE]

As someone said somewhere:

"ST seems to rely more on people using CubeMX instead of correct and detailled documentation."

When the RMs have more than 2000 pages that is not such a bad idea, but sometimes it would be nice to find things a little clearer and more reliable on paper.

[LCE]

So, anybody ever did this?

[Alex - APMemory]

Hi,

Just general comment about H723, H725, H733, H735. they are supporting OSPI, but have limitation with QSPI SDR (no memory mapped write), QSPI DDR OK. We have confirmed testing APMemory RAM

Alex

[LCE]

@Alex - APMemory​ thanks for your input, perfect timing! :)

I just started working with:

• a H735 Discovery Kit with OctoSPI HyperRAM, and
• some H723 Nucleos + APS6404L which is SDR :(

Within the next few weeks I plan to test these memories with the application mentioned above:

SAI_DMA -> external serial RAM -> ETH_DMA

so I definitely need the memory mapping for writing.

Does AP offer any Quad/Octo SPI DDR RAM ?

[Alex - APMemory]

Hi,

We are supporting OPI in BGA24/WLCSP, QSPI DDR in WLCSP only and QSPI SDR in SOP8/USON8/WLCSP. You can find most of them at Mouser for prototyping, such as for example : 128Mb OPI BGA24 3V APS12808L-3OBM-BA, 16Mb QSPI SDR SOP8 APS1604M-3SQR-SN. (128Mb QSPI DDR WLCSP 350um pitch APS12804O-DQ-WA is under NDA)

Alex

[LCE]

@Alex - APMemory​ thanks again, although it's bad news again... ;)

So I will probably not even test the APS6404, and for prototyping BGA s***s.

2 more quick questions, please:

1. Do you have any of the 3.3V DDR types on breakout.boards for prototyping?
2. Is there already a kind of industry standard for tha BGA / WLCSP package and pin layout, so that the user can switch easily between manufacturers?

[Alex - APMemory]

Hi,

We don't have breakout board inhouse. BGA24 is standard among multiple Flash & RAM OPI suppliers. WLCSP is specific to each die.

In case

fyi, probably not for your case, if you use a board with CRUVI connector (Trenz FPGA for example, they have memory CRUVI daughter board supporting full speed memory (with our 256Mb OPI APS256XXN-OBR-BG) (https://shop.trenz-electronic.de/de/CR00045-01-0-CRUVI-AP-Memory-x8/x16-Xccela-PSRAM-Board?c=578)

Regards

Alex