STM32H7 + LwIP: Problems with MPU and Custom Heap at 0x30008000 – No Packets Received

https://www.youtube.com/watch?v=Lpkt-nffVvA&feature=youtu.be

LWI_GUYAuthor

Visitor II

Thanks for your reply.
I will be able to test the MPU configuration in a few days and I will come back to it.

A

avinash_elec

Graduate

A

avinash_elec

Graduate

Please check out my tutorial on setting up lwIP on STM32F7 Series using CubeIDE

https://www.youtube.com/watch?v=A8ii-t40r-w

Technical Moderator

hello @LWI_GUY and @Vangelis Fortounas ,

Please use </> button to share a code. See How to insert source code.

Thank you for your undestanding.

LWI_GUYAuthor

Visitor II

Hi everyone,

I just wanted to give you a quick update on this issue.

I tried your suggestions regarding the MPU configuration and the faulty memory region. However, the same issue still persists.

The code fails in the following section of mem.c within the LWIP stack:

memset(ram, 0, MEM_SIZE);
/* initialize the start of the heap */
mem = (struct mem *)(void *)ram;
mem->next = MEM_SIZE_ALIGNED;
mem->prev = 0;
mem->used = 0;

There’s still a failure when assigning the variable mem, as the specified memory region does not get updated. It does get updated when I disable MPU region 2.

That said, I managed to get ARP working by modifying the code in ethernetif.c, specifically in the low_level_output() function. Here is my current version of the function:

static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
 uint32_t i = 0U;
 struct pbuf *q = NULL;
 err_t errval = ERR_OK;
 ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0};

 memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef));

 for(q = p; q != NULL; q = q->next)
 {
 if(i >= ETH_TX_DESC_CNT)
 return ERR_IF;

 Txbuffer[i].buffer = q->payload;
 Txbuffer[i].len = q->len;

 // New code beginning
 uint32_t addr = (uint32_t)q->payload;
 uint32_t aligned_addr = addr & ~0x1F;
 uint32_t end_addr = addr + q->len;
 uint32_t aligned_len = ((end_addr - aligned_addr + 31) & ~0x1F);

 SCB_CleanDCache_by_Addr((uint32_t *)aligned_addr, aligned_len);
 // New code ending

 if(i>0)
 {
 Txbuffer[i-1].next = &Txbuffer[i];
 }

 if(q->next == NULL)
 {
 Txbuffer[i].next = NULL;
 }

 i++;
 }

 TxConfig.Length = p->tot_len;
 TxConfig.TxBuffer = Txbuffer;
 TxConfig.pData = p;

 HAL_ETH_Transmit(&heth, &TxConfig, ETH_DMA_TRANSMIT_TIMEOUT);

 return errval;
}

I’ve marked the newly added code using comments.

What I’m still wondering is why this cache-cleaning code is necessary here and why the MPU setup doesn’t seem to work as expected.

P

Pavel A.

Super User

As stated earlier, your MPU regions 1 and 2 are invalid and can cause UB. Base address of a region must be aligned on its size.

LWI_GUYAuthor

Visitor II

Hi Pavel,
below is the updated MPU configuration, which I was also using for the post above:

void MPU_Config(void)
{
 MPU_Region_InitTypeDef MPU_InitStruct = {0};

 /* Disables the MPU */
 HAL_MPU_Disable();

 /** Initializes and configures the Region and the memory to be protected
 */
 MPU_InitStruct.Enable = MPU_REGION_ENABLE;
 MPU_InitStruct.Number = MPU_REGION_NUMBER0;
 MPU_InitStruct.BaseAddress = 0x0;
 MPU_InitStruct.Size = MPU_REGION_SIZE_256KB;
 MPU_InitStruct.SubRegionDisable = 0x87;
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
 MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

 HAL_MPU_ConfigRegion(&MPU_InitStruct);

 /** Initializes and configures the Region and the memory to be protected
 */

 MPU_InitStruct.Number = MPU_REGION_NUMBER1;
 MPU_InitStruct.BaseAddress = 0x30000000;
 MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
 MPU_InitStruct.SubRegionDisable = 0x0;
 MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

 HAL_MPU_ConfigRegion(&MPU_InitStruct);


 /*
 MPU_InitStruct.Number = MPU_REGION_NUMBER2;
 MPU_InitStruct.BaseAddress = 0x30008000;
 MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
 MPU_InitStruct.SubRegionDisable = 0x0;
 MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;

 HAL_MPU_ConfigRegion(&MPU_InitStruct);
 */


 /* Enables the MPU */
 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

}

When I enable Region 2, I get the behavior as described above. Region 1 seems to be working fine.
I can't see where I might have made a mistake in the MPU configuration.

Technical Moderator

Hello,

Question: why are you setting the MPU background region size to 256k?

 MPU_InitStruct.Number = MPU_REGION_NUMBER0;
 MPU_InitStruct.BaseAddress = 0x0;
 MPU_InitStruct.Size = MPU_REGION_SIZE_256KB;
 MPU_InitStruct.SubRegionDisable = 0x87;

That region needs to be 4G:

 MPU_InitStruct.Number = MPU_REGION_NUMBER0;
 MPU_InitStruct.BaseAddress = 0x0;
 MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
 MPU_InitStruct.SubRegionDisable = 0x87;

P

Pavel A.

Super User

> why are you setting the MPU background region size to 256k?

In that code, region 0 is not the background. It probably catches null pointer references.

Technical Moderator

This setting means that the MPU config was used as a background region:

MPU_InitStruct.SubRegionDisable = 0x87;

LWI_GUYAuthor

Visitor II

Hi everyone,

I've noticed that I don't need the extra code in ethernetif.c, and I also don't need to adjust the background region of the MPU.

However, for everything to work properly, I currently need to disable the Data Cache entirely.
That said, I would like to enable the Data Cache in my upcoming project, where I plan to use a REST API to control the STM32 and retrieve data.

Unfortunately, I can't get it working properly when I define MPU regions to manage caching behavior. Does anyone know why the STM behaves like this?

I do understand that enabling the Data Cache can lead to inconsistencies between the CPU cache and RAM, especially since the Ethernet DMA won't see the updated data. But why doesn't it help to define MPU regions correctly to disable caching just for the buffers used by the DMA?

Any ideas or experiences with this would be greatly appreciated.