STM32L0 RCC_AHBLPENR and RCC_APBxLPENR registers

[After Forever]

From RM0377:

6.3.3 - Peripheral clock gating

...

...

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBLPENR and RCC_APBxLPENR registers (x can 1 or 2).

I can't find the definitions of these registers anywhere in CMSIS / LL / HAL, neither any other mention of them in the RM.

The only place I've found them being used is in stm32l0xx_hal_rcc_ex.h, in these macros:

#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) != 0U)
#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) == 0U)

[waclawek.jan]

These registers appear to be renamed in the 'L0 series to RCC_AxBySMENR (SM standing for Sleep Mode, instead of LP = Low Power)

JW

[waclawek.jan]

The nonexisting AxByLPENR registers are mentioned also in the 'L0 RMs, e.g.

(note also the cumbersome "x can 1 or 2" formulation).

The reason for change probably is, that these registers function as *masks* to the "normal" AxByENR registers, contrary to the AxByLPENR registers in other STM32 models, which function as *replacement* of the "normal" AxByENR registers during appropriate lowpower modes.

However, I'm not sure if I am correct in this, as in the description of some of the AxBySMENR bits the reference to the "masking" is missing (CRC, SRAM, DMA, CRYPT,. NVM, SYSCFG). Also, it would be nice if this would be clearly described in the chapter the screenshot above is taken of.

@Imen DAHMEN​ ,

can this please be clarified, and documentation fixed accordingly?

Thanks,

JW