STM32N6 cache operations inside noncacheable memory

[ERROR]

Hi,

Looking into STM32CubeN6\Projects\STM32N6570-DK\Examples\SD\SD_ReadWrite_DMA example,
I see that quite heavy operations are used:

SCB_CleanDCache_by_Addr (aTxBuffer, BUFFER_SIZE);
// ...
SCB_InvalidateDCache_by_Addr (aRxBuffer, BUFFER_SIZE);

while the aRxBuffer[] and aTxBuffer[] are located in a noncacheable memory region.

uint8_t aTxBuffer[BUFFER_SIZE]__NON_CACHEABLE;
uint8_t aRxBuffer[BUFFER_SIZE ]__NON_CACHEABLE;

Could you please explain why?

Regards,
A

[Saket_Om]

Hello @ERROR 

Thank you for bringing this issue to our attention.

I reported this internally.

Internal ticket number: 213510 (This is an internal tracking number and is not accessible or usable by customers).

[ERROR]

Hi @Saket_Om 

Is there any update?

Regards.

[Saket_Om]

Hello @ERROR 

The issue has been resolved internally by removing the __NON_CACHEABLE attribute from the buffer declarations, as shown below:

/******** SD Transmission Buffer definition *******/
uint8_t aTxBuffer[BUFFER_SIZE];
/**************************************************/

/******** SD Receive Buffer definition *******/
uint8_t aRxBuffer[BUFFER_SIZE];
/**************************************************/

The fix will be available on st.com in the next release.

 

[Tesla DeLorean]

Presumably for illustration of method for cache coherency.

Would depend on Linker Script and suitable memory region allocation and MPU configuration. 

[Saket_Om]

Hello @ERROR 

The fix has been released with STM32CubeN6 V1.3.0, now available on st.com.