STM32U5A5ZTJ USB PCD failing on initialization at USB_CoreReset()

[JMarple1]

Hello,

I have a Nucleo-U5A5ZJQ dev board and am attempting to get a minimum USB HS example working using the PCD HAL library.  When `MX_USB_OTG_HS_PCD_Init()` is called, a HAL_TIMEOUT occurs when attempting a CoreReset using the `USB_OTG_GRSTCTL_CSRST`, specifically this line in stm32u5xx_ll_usb.c

 /* Core Soft Reset */
 count = 0U;
 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;

 do
 {
 count++;

 if (count > 200000U)
 {
 return HAL_TIMEOUT; <---- THIS LINE
 }
 } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);

 return HAL_OK;

I have checked and confirmed that the USBPHYCEN and OTGEN bits are set in the AHB2ENR1 register before this function call.  I have also confirmed that OTGHSPHYCR is enabled and set to 16Mhz (the USB PHY clock speed). 

I'm currently out of ideas on what would be causing the USB peripheral to fail on initialization.  My intuition is saying that it's clock related, but as far as I can tell, I have setup the clocks correctly according to the datasheet. 

I've attached my project below. Any thoughts would be very much appreciated!

[TDJ]

@JMarple1 I have exactly the same problem. After changing config from HCD to PCD (host to device) the code times out waiting for the OTG_GRSTCTL.CSRST register field to get cleared.

Btw, I am wondering if USB_CoreReset() function code is correct since RM0456, p. 3311 states:

"Once this [CSRST] bit has been cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). The software must also check that bit 31 [AHBIDL] in this register is set to 1 (AHB Master is Idle) before starting any operation."

It seems that the above indicates that first CSRST needs to be set and cleared and then AHBIDL high state should be awaited, not the other way around.

[Riscy]

I have the same problem as Device CMC_ACM from the new code (not the demo code). Have you tried above fixes, does it work? 

[JMarple1]

The above fix didn't work unfortunately and we never ended up resolving this problem.  We've since moved away from USB on the U5. 

[TDJ]

@Riscy, @JMarple1, I got it working, those three posts may shed some light:

• Why OTG_HS USB/USBX Host on STM32U5Axx just does n... - STMicroelectronics Community
• Nucleo U5A5ZJ-Q USBX - Ux_Device_CDC_ACM MX_USB_OTG_HS_PCD_Init() timeout with MSIS · Issue #34 · STMicroelectronics/STM32CubeU5 (github.com)
• USBX Host examples - general issue · Issue #30 · STMicroelectronics/STM32CubeU5 (github.com)

I shared complete, working solution for Nucleo STM32U5A5 here:
tdjastrzebski/Nucleo-U5A5ZJ-USBX (github.com)
Just keep in mind board needs to provide USB-C power. For that undocumented SB8-10 jumpers need to be shorten, additional JP6 jumper in 5V_USB_C position is required.

[Riscy]

Thank, I give a it go :)

 

[TDJ]

@Riscy Since more engineers seem to be interested in this topic and ST is not helpful, I placed my solution on GitHub and added some pics tdjastrzebski/Nucleo-U5A5ZJ-USBX (github.com)

[Riscy]

I have placed the code __HAL_RCC_SYSCFG_CLK_ENABLE(), as shown below, and the CSRST issue went away, but I do not see the COM port on my laptop. It seems the config clock was left disabled before configuring. I review it later in the week and maybe make a fresh Device CDC_ACM project from Cube IDE/MX V140/V141. I have applied PLL1P/2 and RTC enabled.

 

void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd)

{

  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};

  if(hhcd->Instance==USB_OTG_HS)

  {

  /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();

  /* USER CODE END USB_OTG_HS_MspInit 0 */

 

From Palm LLM: The HAL_RCC_SYSCFG_CLK_ENABLE() function enables the clock for the System Configuration Controller (SYSCFG) in STM32U5 microcontrollers. The SYSCFG peripheral is responsible for configuring and managing various system-level features such as power management, clock control, and interrupt handling. By enabling the SYSCFG clock, you can access and control these features through the HAL library functions.

 

[Riscy]

I'm quite puzzled how the CDC_ACM demo code dated 2021, working fine (no issue with USB corereset) that gets away without this statement, __HAL_RCC_SYSCFG_CLK_ENABLE();

I have looked into both 2021 (demo) and 2024 (V141) and still could not find something that activates the syscfg clock to work.

Do I need to disable SYSCFG_CLK after that is done? What is the best place to do this?   

[FBL]

Hello @TDJ 

Thank you for bringing to our attention. An internal ticket is submitted to include these details in HW setup in UM2861 as stated in schematics. 

Internal ticket number: 171723 (This is an internal tracking number and is not accessible or usable by customers).

[Riscy]

I was wondering what change in the schematic. Two separate sheets for host and device configuration or ???

During yesterday's investigation effort to explain why COM does not appear on the device manager in the Windows PC, which led to the reported 2nd issue via this link, the USB failed to start because the callback is not triggered (but the interrupt is working).  I have attached the IOC file to this link. I try to investigate deeper the next day, but I welcome any suggestions. 

https://community.st.com/t5/stm32-mcus-embedded-software/stm32u5a5ztj-usb-pcd-failing-on-initialization-at-usb-corereset/td-p/588493