SVD file of the STM32H753 seems erronous compared to the stm32h753xx.h.

[ZiggyS]

The DFSDM section 29.7 channel configuration register has an offset for each channel of 0x20*y while the SVD file has a 0x4 offset between the channels. Can somebody state the correct offset?

SVD:

...

     <name>DFSDM_CHCFG0R1</name>

     <displayName>DFSDM_CHCFG0R1</displayName>

     <description>DFSDM channel configuration 0 register

     1</description>

     <addressOffset>0x0</addressOffset>

.....

     <name>DFSDM_CHCFG1R1</name>

     <displayName>DFSDM_CHCFG1R1</displayName>

     <description>DFSDM channel configuration 1 register

     1</description>

     <addressOffset>0x4</addressOffset>

.h

...

#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)

#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)

#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)

#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)

#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)

#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)

#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)

#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)

-Z

[Imen.D]

Hello @Sigbjørn Kolberg​ ,

You are right, the svd file is wrong.

We raised this issue internally for fix in the coming release.

Thanks for highlighting this issue.

Best Regards,

Imen

[JHoll]

Any signs of this fix coming soon? I'm porting code from an F4 to an H7 and really need to see what's happening in the DFSDM system.

Regards,

Jason

[Imen.D]

Hello,

Please find attached the updated STM32H753.svd file.

Best Regards,

Imen