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Visitor II
July 6, 2020
Question

tcpip thread message fetch is not running in lwIP if caches enabled in STM32F767

  • July 6, 2020
  • 3 replies
  • 839 views

tcpip thread message fetch is not running in lwIP if caches enabled in STM32F767.

 /* Enable I-Cache---------------------------------------------------------*/

 SCB_EnableICache();

 /* Enable D-Cache---------------------------------------------------------*/

 SCB_EnableDCache();

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    3 replies

    Super User
    July 6, 2020

    Cache management is nontrivial. You can either disable it, or learn how to handle it properly.

    https://community.st.com/s/article/FAQ-DMA-is-not-working-on-STM32H7-devices

    RBGAuthor
    Visitor II
    July 13, 2020

    Can i get the working example code with lwip.

    I feel the problem is lwIP driver Rx data buffers not aligned to cache line size. The address and size of buffers, on which D-cache invalidation are used, must be aligned to __SCB_DCACHE_LINE_SIZE, which is 32 bytes for Cortex-M7.

    So expecting properly aligned buffers example code for STM32F767 with lwip for the reference.