Timer Output Compare Fast Enable not doing what I think it should according to manual, ask for simpler/alternative explanation

[ilyus]

Playing with STM32F746 disco, CMSIS-only, directly with registers, in C. CubeIDE 1.8.0, Win10. Gives a good intuitive understanding of how things work. For now, I'm practicing cascading the Timers in various ways (successfully). The thing I failed to understand is "Output Compare Fast Enable".

My test project works the following way:

1) Timer1 is in one pulse mode. As soon as it has counter enabled, it outputs TRGO. So starting Timer1 also starts Timer3.

2) Timer3 is a slave of Timer1 and is a trigger mode slave (counter enables) immediately as Timer1 has counter enabled. Timer3 is in PWM2 mode (counts up, output low while CNT<Compare1), output Channel 1 to PB4

3) When Timer3 CNT=Compare1, Timer3 makes TRGO and triggers (counter-enables) Timer5 in PWM2 mode, output Channel 4 to PI0

Everything works perfectly exactly as I want, I have no problem with any of that.

What I don't understand is the definition of the Output Compare Fast Enable. I simply want to try out this function to understand what it does, and it doesn't do what I expect.

From STM32F746 Reference Manual RM0385, page 800:

Bit 2 OC1FE: Output compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is

ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is

5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC

is set to the compare level independently from the result of the comparison. Delay to sample

the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if

the channel is configured in PWM1 or PWM2 mode.

My logic: if I make output compare fast enable for the Timer3, then Timer5 must also start immediately when Timer3 starts, because "An active edge on the trigger input acts like a compare match on CC1 output" (channel numbers taken into account!). But I didn't notice any difference in behavior with the scope .I understand I won't see difference between 3 clock cycles and 5 clock cycles on the scope (MCU @ 216MHz), but I was expecting TIM3 and TIM5 to start at the same time according to definition from the manual (Trigger Input becomes automatic Compare Trigger Output regardless of CNT), and that I can totally see with the scope. Except it doesn't happen.

Here is the output of TIM3 and TIM5.

TIM3 in blue, TIM5 is yellow.

Conclusion: I obviously don't exactly understand what output compare fast enable does. Can anyone give alternative explanation of what happens when I use it?

[waclawek.jan]

TRGI through FE sets given OCxREF (which should be visible on the output pin), but probably does not generate the CCx event which would then be output as TRGO.

Read out and post content of TIM registers for further discussion.

JW

[ilyus]

Actually, now the thing worked. There is a momentary pulse in the beginning (TIM3 goes low for 2us - with 2kHz clock! - and then the whole firs period is HIGH), and it actually IS activating TIM5 immediately now. All I did was clean up some code, remove Fast Enable everywhere I had it, and put it specifically on TIM3 again (to pass TIM1 enable through to TIM5). And it did indeed have the whole 1st period as HIGH, setting off TIM5 right away. Seems like I actually got everything right, just overlooked or missed something on software side. Thanks for giving a reason to look through stuff again and make sure it's all correct, it fixed it. I think, fundamentally I understood what it is and what it does, and this was the whole purpose of this question. Many thanks.