Triggering the Update Interrupt Flag of a One Pulse Timer with software

[danielbathtub]

Hi, 

I would like to, trigger an update event interrupt using software. 

My timer runs in One Pulse mode, the idea is, that another event should also run the code in my Timer ISR. 

So after this other event happens in my code, I don't want to wait for the timer, I simply want to trigger the ISR through software, Reset the counter and then stop the counter (this is automatic in One Pulse Mode). 

 

I have tried setting the Update Event Bit in the Event Generation register, without any luck. 

Thanks 

[waclawek.jan]

Maybe others can follow you, I can't. Can you please sketch a timing diagram of what do you have to achieve?

> I have tried setting the Update Event Bit in the Event Generation register, without any luck.

What does "luck" mean here, and how do you know you were without it?

JW

[danielbathtub]

It is really simple what I want to achieve. 

I want to be able, to write a register in Software, which aborts the timer pulse in one pulse mode. 

And disables the timer. For Example if the timer normally outputs a 200 uS Square Wave, I want to be able to shorten this square wave to 50 uS using software when there is a specific event in my software, in my case this is a Analog Watchdog 2 interrupt. So I want to "Abort" the pulse.

Or Just simply write a register which will trigger the update interrupt, so I can run the code in the Timer ISR, and then disable the Timer.

So let me simplify it for you further to a single sentence: 

I need to trigger an update interrupt, with software, for a timer running in One-Pulse Mode.  

 

1. ---

   @waclawek.jan wrote:
   

   Maybe others can follow you, I can't. Can you please sketch a timing diagram of what do you have to achieve?

   > I have tried setting the Update Event Bit in the Event Generation register, without any luck.

   What does "luck" mean here, and how do you know you were without it?

   JW

   ---

The Debugger shows that setting the UG bit doesn't make the code vector into the ISR. 

NOTE: 

{ Don't tell me to use Timer 1 with AWD2 ETR clearing source, I am already using this timer for something else which is far more important. }, 

DanBTubs

 

[waclawek.jan]

Which STM32 and which timer?

> The Debugger shows that setting the UG bit doesn't make the code vector into the ISR.

This is strange. Can you please post the TIM registers content?

> Don't tell me to use Timer 1 with AWD2 ETR clearing source

Well, that was exactly what I was about to propose, as it's intended exactly for this purpose :)

But you should always be able to "reset" the counter manually, by clearing TIMx_CR1.CEN=0 and then TIMx_CNT=0.

JW

[danielbathtub]

 

Note that this is an application where I don't really know the state of the Timer when I want to do this...  

And everything happens at extreme speeds (ISR) triggering. ~1.2 uS. And all the ISR's trigger simultaneously. 

The timer can also trigger it's ISR within another ADC ISR. 

So for me to send you these Debug registers is a waste of time, My OPM timers are about 15 uS and 200 uS. 

So the debugger is really useless, you can see it for yourself if you don't believe me. 

I'll try your suggestions and see if it works.

Thanks

DanBTubs. 

[waclawek.jan]

You can set a breakpoint in the ADC WD ISR, and if you set the appropriate DBGMCU flag to stop TIM when in breakpoint, TIM registers will reflect their genuine state upon executing the ADC ISR.

I was mostly interested in the reason why wouldn't setting TIMx_EGR.UG trigger an Update interrupt, what is what you appear to say. There's the TIMx_CR1.URS bit which would prevent that, do you set it?

JW