Unable to re-configure OSPI Delay Block on STM32U585

[VPham.11]

On our custom board, we have the SoC communicate with the HyperRam Cypress S27KL0641. We followed the example DLYB_OSPI_NOR_FastTuning and OSPI_HyperRAM_MemroyMapped. The device is working properly on the first initialization. But if we call Deinit and reinitialize the OSPI, the function LL_DLYB_GetClockPeriod() always return ERROR or timeout. However, if we reset the whole system, then the function LL_DLYB_GetClockPeriod works fine first time. What would've caused this issue ?

[Mohamed Aymen HZAMI]

Hi @VPham.1​,

Sorry to come back with some delay to your question, but it is important for us to know if you still face an issue or not?

If yes, could please confirm if the same issue is faced when using ST board with STM32Cube examples? Did you tested your own examples on ST board?

Aymen

[VPham.11]

Yes we still have the issue.

No we haven't tried the example on our custom board.

Would you happen to know if there are anything we can take a look at or anything we can do to give you a clue to figure out the problem ?

[LCE]

I'm using a H735, no problem here using direct register access.

/* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* OCTOSPI1 clock delay block */
uint8_t OctoSpi1ClkDlyON(uint32_t u32Delay)
{
	if( OctoSpi1CheckBusy(QSPI_TIMEOUT_BUSY_MS) )
	{
		uart_printf("# ERR: OctoSpi1ClkDlyON(): OCTOSPI_SR_BUSY\n\r");
		return 1;
	}
 
	/* disable the output clock and enable the access to the phase selection SEL[3:0] */
	DLYB_OCTOSPI1->CR 	= DLYB_CR_SEN;
	/* set delay */
	DLYB_OCTOSPI1->CFGR = u32Delay & DLYB_CFGR_SEL_Msk;
	/* disable the access to the phase selection, enable output */
	DLYB_OCTOSPI1->CR 	= DLYB_CR_DEN;
 
	/* enable in peripheral -> clear bypass */
	OCTOSPI1->DCR1 &= ~OCTOSPI_DCR1_DLYBYP;
 
	return 0;
}
 
uint8_t OctoSpi1ClkDlyOFF(void)
{
	if( OctoSpi1CheckBusy(QSPI_TIMEOUT_BUSY_MS) )
	{
		uart_printf("# ERR: OctoSpi1ClkDlyOFF(): OCTOSPI_SR_BUSY\n\r");
		return 1;
	}
 
	/* disable in peripheral -> set bypass */
	OCTOSPI1->DCR1 |= OCTOSPI_DCR1_DLYBYP;
 
	/* disable delay block */
	DLYB_OCTOSPI1->CR 	= DLYB_CR_SEN;
	DLYB_OCTOSPI1->CFGR = 0;
	DLYB_OCTOSPI1->CR 	= 0;
 
	return 0;
}