USB SOF period incorrect in host mode during CSleep on STM32H743

[CHead]

My OTG_HS2 kernel clock is PLL3Q at 48 MHz. If I use CSleep (only CSleep, not any of the deep sleep modes), SOFs are generated at the wrong interval (checked with protocol analyzer and oscilloscope). If I remove the WFI, SOFs are generated at the proper interval. It seems that either CSleep is gating the USB clock or else it is turning off PLL3, neither of which it should do. Has anyone else seen this?

[CHead]

Clarifying comment: lots of other USB things, not just the SOF period, seem to be broken by CSleep.

[antej]

You probably don't needed an answer anymore but it may help the community.

If you use the internal STM32 USB PHY you must disable the ULPI clock in CSleep mode (by setting the USBxOTGHSULPILPEN bit of the RCC_AHB1LPENR register to 0) which is not the case by default.