UsbX memory split memory pools

[matt-crc]

Hello,

I was looking at the UsbX middleware source code and noticed that the memory pools are split in 2. 

a) non-cached memory pool

b) cached memory pool

The STM implementation doesn't seem to use this code and just places everything into the non-cached memory pool.

So my questions are:

1- has anyone used the split memory pools, and does it actually work? -OR- it doesn't work and that's why it was disabled by ST.

2- if it is enabled, how much of a performance boost will it provide? and is it worth the time and effort to split the pools?

thanks, Matt

 

[FBL]

Hi @matt-crc 

Only non-cached memory to be used to ensure cache coherency on STM32 products with Data cache support.