Watchdog reset the CPU when CPU is halted.

[RahulPatil_123]

On nucleo_u575zi_q below observations has been captured.

Issue: - when IWDGRSTF flag is cleared by writing to the RMVF bit still watchdog reset occurred.
Expected Behavior: - When the IWDGRSTF flag is cleared by writing to the RMVF bit, the watchdog reset should not occur.

Please find the below snippet of sample code of STM32cubeIDE.

Also find the reference of user Manul and data sheet of nucleo_u575zi_q board.

Please provide appropriate solution for the above issue.

[Ozone]

> Expected Behavior: - When the IWDGRSTF flag is cleared by writing to the RMVF bit, the watchdog reset should not occur.

Why do you expect such a behavior ?
Nowhere is stated that any access to said flag will stop the IWDG.

[RahulPatil_123]

 

LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP);

what is meaning of above snippet code and above function can you please explain?

 

what does the below micro

 DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos) 

[TDK]

To halt IWDG during debug, set DBG_IWDG_STOP in DBGMCU_APB1LFZR.