What are the timing constraints on BOOT0 and \RESET ?

[JCase.1]

I need to know the timing constraints for bootloading (over UART). How long must \RESET be held low to reset? How long must BOOT0 remain high after \RESET is released? I need this for the STM32L4P5, the STM32F423, and the STM32G031. I apologize in advance, since it is certainly published somewhere, but I couldn't find it.

[AScha.3]

so here from ds+rm F303 , cortex M4 core :

reset:

and boot mode set:

 

• reset min 20us , to be shure, i would make 10ms and fine.
• boot is set after 4 sysclks after reset...i would make > 1ms and fine.
• to be shure, for your different chips, look in the respective manuals (timings might be different)