Why is the ADC calibration procedure for STM32F107 different from datasheet?

[Kazimierz Król]

I am currently writing code for STM32F107VC CPU, and I want to use ADC, calibrating it first. I have noticed a strange thing in the ST HAL library.

The datasheet on page 223 reads "Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’) for at least two ADC clock cycles."

However in the firmware for this CPU (stm32f1xx_hal_adc_ex.c) the function HAL_ADCEx_Calibration_Start first disables the ADC, then waits for 2 ADC clock cycles. It doesn't wait after enabling the ADC again. The comment in the code says "Calibration prerequisite: ADC must be disabled for at least two ADC clock cycles in disable mode before ADC enable". And the code that follows there disables the ADC (clears ADEN bit).

Why does the HAL code wait two ADC clock cycles after disabling the ADC, when the datasheet clearly says it should wait after enabling the ADC? Is this intentional for some reason (I checked the errata, but couldn't find anything), or did the author of this function misunderstood the datasheet?

[Mike_ST]

Hello,

Not clear for me as well.

I have opened an internal question.

(#142465)

[Mike_ST]

Hello,

I have got a first answer.

"RM0008 Rev21 section 11.4 ADC Calibration is correct."

Following the question, the maintenance team has opened a defect ticket (#142574).

So I guess it will be fixed in a later STM32F1 software package delivery.

Thank you for this report.

[Mike_ST]

Update: Fix delivered in STM32Cube_FW_F1_V1.8.5