Why must VDDUSB be lower than VDD during both power-on and power-off?

[Tone]

What would happen if this requirement is not met?

Reference:

According to the STM32F777xx STM32F778Ax STM32F779xx datasheet (DocID028294 Rev 6), page 28:

"- During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD

- During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD"

[waclawek.jan]

There are probably internal diode-like structures between VDD and VDDUSB, which when you reverse them, might let through enough current to damage themselves.

Above VDD_MIN, the reset circuitry might activate switches which reliably decouple the two.

JW

[PLaid.1]

In another post a user states that this is a requirement only if the power supplies are not tied together. In My case, I'm using a STM32L072 in a package with a LoRa transceiver and the specification clearly states the (lower voltage) requirement without any language referring to the nature or source of the VDD_USB power.

I'm going with the notes provided in STM AN4879 Section 2.5 that states that it is not a requirement when they are tied together. I hope it's right!

[Tesla DeLorean]

Ok, but we don't cite that post, and this one is for another part, which is a different design on a different process.

The L series parts being particularly different in they have an expectation of a battery supply (ie also no VBAT), and run voltages that can get very low.

if VDD == VDDUSB, bonded externally, there's really no conduction paths.

The case they want to avoid is VDDUSB in the absence of VDD / VDDA. That if you have a USB connection, that you use that as a primary source, or as a means to charge/supplant the battery.

VDDUSB exists so that the switching voltages of DP/DM meet USB Standard Specifications, and this supply is acting as the source for the IO Cells involved. There will be ESD diodes, and these will provide conduction paths that can potentially back-power the entire device. This gets into the internal implementation, and might perhaps be something to discuss with you local FAE, in the context of the devices you are using.

[PLaid.1]

Thanks very much for this; I think I'm OK in my design then: I see your point on DP/DM switching voltages in circumstances where a battery could be quite low. In my case everything is switch regulator powered at 3.3v from either battery or USB. That is; all VDD_*** are at common 3.3v regardless of power source as is DP/DM and the power connection to the diode protection array.

I have not identified an application engineer for this and I experience a small complication when multiple manufacturers products are integrated into a functional block. I rely on forums like this one for help and I'm forever thankful.