Write to TIMx break and dead-time register

[Locnvselex_vn]

Hello everyone!

During programming for the MCU STM32G431CbTx, I want to write a function to change the value of the "Break filter" bit for "Tim_BRK" as follows:

 

static inline void mcu_protection_ov_enable_filter(){
 uint32_t tmpbdtr = READ_REG(TIM1->BDTR);
 tmpbdtr = (tmpbdtr & 0xFFF0FFFFU) | LL_TIM_BREAK_FILTER_FDIV2_N8;
 WRITE_REG(TIM1->BDTR,tmpbdtr);
}

 

 

However, after checking, the value of the BKF bit remains unchanged, while the LOCK bit is set to 00: LOCK OFF - No bit is write-protected. Meanwhile, I can use a similar method to change the DTG (deadtime) bit.

Who can support me?

Thanks,

Locnv.

---

Edited to apply code formatting - please see How to insert source code for future reference.

[Sarra.S]

Hello @Locnvselex_vn, 

As described by the RM, you need to configure all relevant bits during the first write access to the TIMx_BDTR register. Try setting the lock bits to 00 in a single write operation 

[Locnvselex_vn]

hello @Sarra.S 

Thank you for your feedback!

Below is the function for configuring the BDTR register of the timer. 

 

ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
{
uint32_t tmpbdtr = 0;

/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));

/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */

/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
if (IS_TIM_ADVANCED_INSTANCE(TIMx))
{
assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
}

if (IS_TIM_BKIN2_INSTANCE(TIMx))
{
assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));

/* Set the BREAK2 input related BDTR bit-fields */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
}

/* Set TIMx_BDTR */
LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); // write 0

tmpbdtr = (tmpbdtr & 0xFFF0FFFFU) | LL_TIM_BREAK_FILTER_FDIV2_N8;
WRITE_REG(TIM1->BDTR,tmpbdtr); // write 1

tmpbdtr = (tmpbdtr & 0xFFFFFF00U) | 100;
WRITE_REG(TIM1->BDTR,tmpbdtr); // write 2

return SUCCESS;
}

In the line labeled 'write 0,' the function initializes the register with the default value where the LOCK bit is 0. The 'write 1' line is intended to modify the BKF bit, but in the debugger, the BKF bit does not change. However, after the 'write 2' line, the DTG bit changes.

Additionally, I also tried modifying the LOCK bit, but it was unsuccessful.