How can I bridge between two cores in STM32H745 to share data?

[Davood_Kesha]

Dear ST team,
I need some tips!!!
I am using STM32H745 for my project. In the project, the M7 core is dedicated to control and measure the power circuit values and M4 core is responsible for communications (few UARTs) and LCD. I configured the MCU with STM32CubeMX and use Keil uvision fore code composing. After generating code, I noticed that there are two separated codes were generated for each CPU.
How can I bridge between two CPUs to share data? I want to send measured data by M7 via UARTs controlled by M4?
I will appreciate if you give me some applicable suggestions.

[mƎALLEm]

Hello,

I invite you to refer to AN5617 "Introduction to inter-processor communications for STM32H745/755 and STM32H747/757 MCUs"

And this knowledge base articles:

1- STM32H7 Dual-Core: How to communicate between CM4 & CM7

2- How to implement inter-processor communication in an STM32H7 using HSEM

3- How to implement inter-processor communication in an STM32H7 using OpenAMP

See also examples based on OpenAMP library available in CubeH7 package: https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Projects/STM32H745I-DISCO/Applications/OpenAMP

PS: I'm changing the thread title to be more concise.

Hope I've answered your question.

Thanks for sharing your setup — this is a common situation when working with the STM32H745 dual-core architecture.

Since M7 and M4 run separate firmware images, the best way to bridge them is by using shared RAM together with a synchronization method. Typically, the M7 core can store measured power data inside a shared memory region (like SRAM3), while the M4 core reads that data and handles UART transmission and LCD updates.

A practical approach would be:

• Use shared memory for the data structure (voltage, current, flags, etc.)

• Use Hardware Semaphores (HSEM) or IPCC interrupts to notify the M4 core when new data is ready

• Let M4 transmit through UART after acquiring the semaphore safely

Also, if D-Cache is enabled on M7, remember to clean/invalidate cache lines, otherwise M4 may read outdated values.

I recently followed a similar workflow while organizing some embedded and game-related technical guides on my site (https://stardewapkvalley.com/stardew-valley-coop/ , and separating control logic from communication tasks made the system much more stable.

Hope this helps — dual-core STM32 projects become much easier once IPC is structured properly :thumbs_up:.

[Andrew Neil]

Sharing data between two cores of H7