STM32 MCUs Products

I’m interested in STM32H5 series (since it’s based on a M33 core which offers performance and security).I need to execute FFT and FIR filtering functions in real time and so I’ve been investigating on hardware accelerators available on the MCU.I see there are CORDIC and FMAC, but I don’t find a specific mention to FFT (like NXP does for PowerQuad).So I wonder if they can be used to perform hardware-optimized FFT.And I wonder if ST has some benchmarks (with sample code) for hardware accelerated FFT on STM32H5.Thanks

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/** ****************************************************************************** * @file Demonstrations/Src/selftest.c * @author MCD Application Team * @brief Main program body ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2016 STMicroelectronics International N.V. * All rights reserved.</center></h2> * * Redistribution and use in source and binary forms, with or without * modification, are permitted, provided that the following conditions are met: * * 1. Redistribution of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of

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Hello all,I’m working with an STM32 microcontroller (specifically the STM32H743), and I have a question regarding the use of an external TCXO as the HSE clock source.As per the datasheet, when using an external clock source (such as a TCXO), the HSE must be configured in bypass mode, and the input clock is expected to meet the digital I/O thresholds (e.g., 0.7 × VDD for logic high). However, many high-quality TCXOs have typical output swings of only 0.8–1 Vp-p (clipped sine wave), which do not meet CMOS thresholds when VDD is 3.3 V.Therefore, directly driving OSC_IN with such a TCXO in bypass mode is not viable per the datasheet.That said, I made an observation I’d like to confirm with you:While using a crystal in crystal resonator mode (not bypass), I probed the OSC_IN pin using a low-capacitance active probe and measured a signal of approximately 1 Vp-p. Since this amplitude is generated internally by the oscillator circuit when using a crystal, it seems the STM32’s HSE input is desi

The STM32L476 does not have an nBOOT0 option bit in its option bytes. Is there a way to boot from the main flash memory without using the BOOT0 pin?

The STM32G031G8U6 in a UFQFPN28 package does not have PF0 / PF1 pins for HSE OSC_IN / OSC_OUT.  It does however have OSC_IN on PC14.  This is intended for an external CMOS oscillator in bypass mode.I’m currently in the schematic design stage. My board clock is a clipped-sine TCXO used for other purposes.  In some modes, I’d like to use it to clock the STM32. I’m very constrained on cost, power, and board space.  The clipped-sine doesn't meet the voltage level requirements for a bypass-mode clock.Is it possible to configure HSE as if it were a crystal, but instead supply a clipped-sine 0.8 Vpp clock from the TCXO to PC14 OSC_IN? Does the die used in UFQFPN28 even have the HSE oscillator circuit that exists in the 48 pin package?I would set RCC_CR[HSEBYP] = 0 and RCC_CR[HSEON] = 1.  I don’t see any register controlling the OSC_IN alternate function on PC14.  STM32CubeIDE doesn't allow this configuration, unsurprisingly, but I would configure t

Hello everyone,   i want to build a CAN FD network with three NUCLEO-C092RC boards. So far i can transmit frames, as i can see on an oscilloscope. But the moment i connect TWO boards, the interrupt is not triggered. My code should activate user LED2 if it receives a frame with one specific id: Board 1 (0x101) triggers LED when receiving message 0x344 or 0x234 Board 2 (0x234) triggers LED when receiving message 0x344 or 0x101 Board 3 (0x344) triggers LED when receiving message 0x101 or 0x234   i use a nom. baudrate of around 500 kbit/s and data baudrate of 1 Mbit/s with a clock of 40 MHz (HSE). The Boards are connected with two short (10cm) twisted jumper cables and the jumpers for the 120 Ohm resistor are also plugged in on both baords. when i test it in external loopback mode, it works (with ident. change) Could this just be a problem with my wires (reflexion , parasi. C ,etc.)?   thanks a lot for the help

Hello. I've a problem regarding LSE On stm32l562xx mcu. Sometimes it boots, sometimes it doesn't "90 % of time it generates timeout Error" . and it takes too much time to boot up to 4 seconds. I've tried all your sdk initializations, also tried setting lse drive to all 4 modes but nothing changes. Same behaviour and same time. Below is my initialization code and attached how we connect LSE on our board. Regards   RCC_OscInitTypeDef RCC_OscInitStruct = {0};  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};  /** Configure the main internal regulator output voltage  */  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK)  {    /*Error*/  }  /** Configure LSE Drive Capability  */  HAL_PWR_EnableBkUpAccess();  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);  /** Initializes the RCC Oscillators according to the specified parameters  * in the RCC_OscInitTypeDef structure.  */  RCC_OscIn

I am working with an STM32F769NI and planning to implement my own Ethernet driver without using the HAL. While studying the DMA descriptor system, I found that the hardware supports both ring structure and chain structure descriptors. However, I am having trouble understanding the exact behavior of the ring structure. For example, suppose I have three TX descriptors: DESC0, DESC1, and DESC2. After the DMA finishes transmitting DESC0, how does it advance to DESC1? Since the descriptor size is fixed, does the hardware simply move to the next descriptor by doing something like: current_descriptor_address + descriptor_size? If that is the case, then I don’t clearly understand what the practical difference is between ring mode and chain mode. So my questions are: In the STM32F769 Ethernet DMA, how exactly does the DMA engine move to the next descriptor in ring structure mode? (I would like to understand this at the hardware/register level.) What is the functional difference betw

Hello,I am working with the B-L4S5I-IOT-01A board (MCU: STM32L4S5VIT6) and attempting to load a .hex file using the UART bootloader via USART1 (PB6, PB7).Since this USART is connected by default to the ST-LINK interface, I removed the necessary resistors (R42, R43) to isolate the ST-LINK connection. I then provided direct RX/TX connections from the MCU side through the corresponding pads.However, I am unable to detect the MCU UART in the STM32 Programmer IDE. The device does not appear or respond during the bootloader communication attempt.Could you please guide me on the correct procedure to:Properly enable UART boot mode on this boardEnsure USART1 is usable for bootloader communicationIdentify any additional hardware or configuration requirementsAny reference or clarification would be greatly appreciated.Thank you.

Dear Forum,I'm using a STM32F401 and implemented the I2C as Target transmitter (Slave) answering a I2C question. I'm programming the I2C CR2 (FREQ Bits) Register as follows with correct speed (42 MHz)I2C1->CR2 = ((DRV_RCC_GetPCLK1Freq() / 1000000u) & I2C_CR2_FREQ_Msk); I've noticed some spikes when the STM32 I2C controller generates the answer, see below (yellow markings)Blue: Clock generated by the controller (the clock speed is about 200kHz)Red: Adrdess Byte generated by the controller, Data Bytes generate by STM32 I2C transmitter (answer) with spikesWhen the FREQ Bits of I2C_CR2 Register are zero, this spikes doesn't occur, see belowThe Reference Manual RM0368 Rev 6 for the I2C CR2 writes:It is noticed that this FREQ bits must be configured to generate I2C compliant Signals. Anyhow from EMC perspective this spikes are bad because the radiate a wide spectrum. I've found nowhere information of correct I2C specifiation/behaviour of the Data Signal the be compliant

Hello, we are seeing a weird symptom in our application in which all LTDC registers are reading back the same seemingly random number.  This is during a debugging session via system viewer (we are using Keil 5.40 and compiler 5), OR when reading and printing out values to serial at runtime.  The LTDC seems to be operating properly (mostly, working through various issues but it's displaying graphics at least.  I'm stumped, and so are the AIs I use.  Any ideas as to why this might be? 

Hello!I am using a 32.768 kHz TCXO (TG-3541CE) as the LSE to count the RTC.The MCU is an STM32L452RE.At room temperature, the RTC operates correctly, but at high temperatures (around 50 °C), the RTC stops.Strangely, once it has stopped, touching the MCU by finger causes the RTC to start running again.Suspecting an issue with the TCXO, I tried a different TCXO, but the same behavior occurred. When I added a 200 Ω damping resistor between the TCXO and the MCU, the RTC no longer stopped even when the temperature was raised to 60 °C.This seems to have solved the problem for now, but I am concerned about whether 200 Ω is an appropriate value and whether this is truly a fundamental solution.If you have any ideas about possible root causes or considerations, I would really appreciate your advice.

Hello everyone, I have a NUCLEO-H755ZIQ board and I am trying to use the HRTIM to output a 50Hz pwm signal. I hook the output to an oscilloscope and I see that the pulse has a period of 19.2ms instead of 20ms, meaning that while I have configured the clock for the HRTIM to run at 2MHz (meaning that it needs 40000 ticks to complete a period) it runs at 2.6MHz. Can anyone help me understand what am I doing wrong? I have attached the .ioc file. Thanks in advance! 

Hi,we are using the internal SMPS for core voltage generation.VDD, VBAT and VDD18AON are on 1.8V. My question is if I can also power up the other 1.8V lines (VDDSMPS, VDDA18USB, VDDA18CSI, VDDCSI,VDDA18ADC and VREF+) simulteanously with VDD, VBAT and VDD18AON or does this harm the device?So I would like to power up the 1.8V lines all together to get rid of an additional load switch on the PCB (for delaying the "late" 1.8V lines) due to space constraints. Is it possible? Thanks a lot!

During the initialization of STM32 UHS-I, it has an IO output of 3.3V. After initialization, it outputs at 1.8V. However, I noticed that the external voltage switch transceiver is powered at 1.8V on the host side. I'm afraid it might burn out the external voltage switch transceiver. Before initializing the SD card, can the SDMMC internally switch to a 1.8V control signal and directly input it to the external voltage switch transceiver? I noticed that the voltage switch transceiver A side recommended in <RM0433> is also powered at a fixed 1.8V. Is there another way to use the SDMMC

Hello ST Community,I’m working with the STM32 Nucleo-N657 board and need a way to execute my application after flashing to external memory without manually toggling the BOOT1 jumper on the board.What I’m Doing Now:BOOT1 jumper is set to HIGH for development (DEV boot mode)I have a simple LED blink application built with GPIO configured in the FSBL context The code runs as expected in DEV mode (debug mode of STM32CubeIDE)I then flashed the signed binary in external memory using STM32CubeProgrammer and External Memory loader for Nucleo-N6 board at address 0x70000000. Then, I switched BOOT-1 jumper to LOW and reset the board. The code runs as expected from external memory.Problem:I have N6 board connected to a remote PC and won’t always have physical access to toggle the BOOT1 jumper and press reset.I would like to know:Is there a programmatic or configuration-based way to run the program automatically after flashing, without needing to change the BOOT1 jumper man

Dear, @halfhalf Post Edited by ST moderator to apply source code formatting and translate from Chinese to English to comply with the community rule:Best regards,Gyessine------------------------------------------------------------------------------------------------------------The STM32G474R datasheet does not mention the BOOT1 pin.If the BOOT0 pin of STM32G474R is set to high, where does the program start?If the BOOT0 pin is set to high and the BOOT1 pin is set to high, the program starts from SRAM. Is the program size limited by the size of SRAM? If a bootloader program and a main program are written, with the bootloader starting at address 0x20000000 and the main program starting at address 0x08000000, can this solve the issue of jumping from SRAM at 0x20000000 to flash memory at 0x08000000, so that the main program size is only limited by the size of flash memory?----------------------------------------------------------------------------------------------------------

Apologies in advance, this is a long one.We are developing a camera application on an STM32H747. We have 32GB of SDRAM configured through FMC.We have a NanEyeC camera from which we are continuously acquiring data in packed bayered format via SPI, into one of three SDRAM framebuffers [A1,A2,A3] (a three-buffer system so that one is reading, one is pending, and one is writing).On our main loop we check to see if one of the raw camera data [A1,A2,A3] has available data and then (1) unpack and debayer it into a 320x320 RGB888 SDRAM framebuffer [B] (we want this intermediate point from which the user can save images), then runs a scaling operation to transfer it into a 460x460 (our display size) RGB888 SDRAM framebuffer [C],After these for loops we start a DMA2D transfer which combines [C] with overlay graphics in 460x460 ARGB4444 SDRAM framebuffer [D], and outputs the result into 460x460 RGB888 SDRAM framebuffer [E], and the DMA2D end-of-transfer interrupt initiates an LTDC-DSI operation w