STM32 MPUs Products and hardware related

Hi,I'm working on to get the multiple SAI to Codec to work synchronized as the connection below,1x MCLK1x BCLK1x FSYNC4x DIN4x DOUTWhere the three Clocks 1x lines (MCLK, BCLK & LRCLK) from one SAI master (actual pinout clock) & other SAI (pinout DIN & DOUT) sync clock internally (not sure possible b/w the SAI).SAI1 (clock master) -> MCLK, BCLK, FSYNC, DIN/DOUT -> codec1SAI2 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec2SAI3 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec3SAI4 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec4According to the TRM RM0436 Rev 7 55.4.4 External synchronization should be used between the SAI.does this need external pin connection between two SAI (all three clocks)? I'm facing error when arecord on SAI1 in the background and trying to start playback on SAI2, attached dts overlay filearecord -D hw:0,0 -f S16_LE -r 48000 -c 2 -d 0 /dev/null &sleep 1aplay -D hw:0,2 -f

Hi everyone,I'm currently validating a custom board featuring the STM32MP257 interfacing a single 16-bit DDR4 at 2133MT/s (Point-to-Point topology). I am using the ST-provided Excel tool ("Examples of DDR memory routing on STM32MP2 MPUs") to extract the Die-to-Ball Package Trace Lengths (mm).I’ve run into a few specific SI conflicts regarding the hardware guidelines, primarily driven by my PCB stackup. Due to routing density, my Address/Command (A/C) signals are split across two different layers:L6 (Bottom Layer): Microstrip. Outer solder mask is 0.6mil (Dk 4.85) over a 3.91mil 3313 Prepreg (Dk 4.4). Effective Dk is much lower due to air exposure.L3 (Inner Layer): Stripline. Sandwiched between a Core (Dk 4.6) and Prepreg (Dk 4.5). Effective Dk is approx 4.5.This leads to the following questions:1. Balancing Physical Length (mm) vs. Electrical Delay (ps): The ST guideline dictates an A/C to CLK_P/N equalization of +/- 140 mils (3.55 mm). However, if I strictly match the physical length

Hi,I recently just finished the Yocto Bringup of a custom STM32MP15FAA1. Everything seems to be working in my application. I am now looking to begin development of the M4 in which I need access to either SWD or JTAG to do lower-level development. Unfortunately, I am having trouble connecting to either interfaces through both CubeIDE and also manually inputting OpenOCD in an IDF Powershell instance.I presume the easiest way to get to my goal is to setup SWD which on the MP15 maps to TMS (SWDIO) and TCLK (SWCLK) and I connected GND and VCC. My STLinkV3-MIME detects 3.3V on the reference line but can never connect to target. This is my first time working with a SOM as most of my development is on base Cortex M microcontrollers so I have a few questions.1. Is there anything in the M4 device tree that can be preventing JTAG from operating like the STPMIC? I do have M4 RPROC enabled in my device tree and the file descriptor is available for me to access.2. Does the boot mode matter? My end a

Hi,I'm designing a board with STM32MP153FAD and have a question about DDR layout reference.Which reference should I follow for the DRAM section?Eval kit MB1272C_03 layoutST's published reference DDR layout.Questions:Which is the recommended reference for custom board design?Is there a design guide specifically for STM32MP153 DDR layout and routing guidelines?Is there a document listing pin delays for the FAD series SoCs? This would be helpful for length matching calculations.Best regards,Batuhan

We have some devices based on STM32MP257 SoCs that connect to a 100 Mbit Ethernet network via ETH1, where ETH1 is going straight to an RMII PHY. Pins for ETH2 are reserved, but are not used/not connected. Some of our devices work rock-solid as excepted, but others exhibit massive performance problems on the Ethernet connection.After lots of research, we think that our devices are affected by a silicon bug described in errata sheet ES ES0598 as "ETH1 RMII mode could have CRC errors". Our chip revisions are all rev Y, which are affected by the issue. The errata says that ETH1 should be routed through ETHSW to work around the silicon bug. To test if the workaround works for our case, I've tried to enable ETHSW, but failed so far because STM32CubeMX forces me to free some pins before it allows me to enable ETHSW in RMII mode. It seems like ETH1 and ETH3 must be used together if ETHSW is enabled, the pins for ETH3, however, are already used for other hardware functions.So, my goal is to- en

Hello,I'm stalling with an issue with Optee on a custom board with 256 MB of ram and an STM32MP135D.The environment was working with the DK (MP135F and 512M ram).I followed the guide for the configuration with 256 MB of ram (https://wiki.st.com/stm32mpu/wiki/How_to_configure_a_256MB_DDR_mapping_from_STM32_MPU_Distribution_Package), however it panics as soon as optee starts.Am I missing something or do you have some hints?Thank you NOTICE: CPU: STM32MP135D Rev.Y NOTICE: Model: STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06 ERROR: nvmem node board_id not found INFO: PMIC version = 0x21 WARNING: VDD unknown WARNING: stm32_rng_init: No RNG found in device tree. NOTICE: Reset reason (0x35): INFO: Power-on Reset (rst_por) INFO: FCONF: Reading TB_FW firmware configuration file from: 0x2ffe0000 INFO: FCONF: Reading firmware configuration information for: stm32mp_fuse INFO: FCONF: Reading firmware configuration information for: stm32mp_io INFO:

Hello,There seems to be an issue with the I2C addresses listed in the MB1854 (B-CAMS-IMX) documentation and schematics (B01/B02).The documents show:IMU: 0xD4 / 0xD5ToF: 0x52However, these appear to be 8-bit addresses. The correct 7-bit I2C addresses should be:ToF (VL53L5CX): 0x29IMU (ISM330DLC): 0x6A / 0x6BThis can cause confusion when using standard I2C tools or drivers.Could you please clarify or update the documentation to specify the address format (7-bit vs 8-bit)?Thanks.

 Hi everyone,I am working on an STM32MP2 platform and facing a persistent issue with LPUART1 in interrupt mode.SetupMCU: STM32MP2UART used: LPUART1 (RS485 communication via MAX485)Debug UART: UART5 (polling mode, printf works fine)Using:HAL_UARTEx_ReceiveToIdle_IT() for RXHAL_UART_Transmit() for TXBaudrate: 115200ProblemWhen using interrupt mode, the system gets stuck in: HAL_UART_IRQHandler()The interrupt keeps triggering continuously and the system appears stuck (infinite IRQ loop).ObservationsPolling mode (HAL_UART_Receive) works perfectlySensor communication works fine in pollingIssue only happens in interrupt modeWhat I already checked NVIC enabled correctly:HAL_NVIC_SetPriority(LPUART1_IRQn, 5, 0);HAL_NVIC_EnableIRQ(LPUART1_IRQn); IRQ handler is correct:void LPUART1_IRQHandler(void){HAL_UART_IRQHandler(&hlpuart1);}No wrong handle (huart1) is used anywhereFIFO configuration added:HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8);HAL_UA

Section 2 of this page shows how to setup python for building firmware.  It seems the rest of the tutorials assume you are building on a modern Ubuntu, so I would suggest changing the following lines:pip install pyelftoolspip install pycryptodomexto:sudo apt install python3-pyelftoolssudo apt install python3-pycryptodomeI would also suggest adding:sudo apt install python-is-python3 My reasons are that you can not/should not install the above packages to the global python environment with pip.  Also, the makefiles for M33 firmware call 'python' which does not exist on a new ubuntu install (well, it didn't on mine).  Installing python-is-python3 is the recommended way to resolve this.  Alternately use a virtual environment, but the firmware build system seems to assume use of the global python.

On the STM32MP135F-DK, is the 4.3" LCD module physically removable? Or is CN16 accessible without removing the LCD?

Are there STM32CubeMX files for the example projects in STM32Cube_FW_MP2?  It would really help understand peripheral configuration.  Specifically the .ioc file for the OpenAMP example project used in this tutorial.I am trying to better understand STM32CubeMX peripheral setup, especially in regard to how each peripheral can be selected for each core in secure or non secure mode.  And how that interacts with the Linux device tree.

I flash the image from FlashLayout_sdcard_stm32mp257f-ev1-ca35tdcid-ostl-m33-examples-optee.tsv pi@inspiron:~/yocto/build-openstlinuxweston-stm32mp2/tmp-glibc/deploy/images/stm32mp2$ STM32_Programmer_CLI -c port=usb1 -w flashlayout_st-image-weston/optee/FlashLayout_sdcard_stm32mp257f-ev1-ca35tdcid-ostl-m33-examples-optee.tsv   I copy stm32mp257f-ev1-ca35tdcid-ostl-m33-examples.dts from the following directory. pi@inspiron:~/yocto/build-openstlinuxweston-stm32mp2/tmp-glibc/work-shared/stm32mp2/external-dt/linux$ ls Makefile stm32mp257f-dk-ca35tdcid-ostl-resmem.dtsi stm32mp135f-dk-rt.dts stm32mp257f-ev1-ca35tdcid-ostl.dts stm32mp157f-dk2-rt.dts stm32mp257f-ev1-ca35tdcid-ostl-m33-examples.dts stm32mp157f-ev1-rt.dts stm32mp257f-ev1-ca35tdcid-ostl-m33-examples-resmem.dtsi stm32mp257f-dk-ca35tdcid-ostl.dts stm32mp257f-ev1-ca35tdcid-ostl-resmem.dtsi stm32mp257f-dk-ca35tdcid-ostl-m33-examples.dts stm32mp257f-ev1-rt.dts stm32mp257f-dk-ca35tdcid-ostl-m33-e

Hi!My Linux is booting on my custom board. This board is using 2 GB (16-bit density) instead of 4 GB (32-bit density).So, when Linux is booted. I get this.Can it be so CubeMX is only fixed to 4GB when selecting STM32MP257F? Any suggestions? The complete log is attached.I'm using USART6 as debugging tool. flags=600, drv->flags=0, err=-129 Sending event 6/(unknown) to spy 'efi_disk del' Sending event 6/(unknown) to spy 'efi_disk del' eth1_clk_mx-0: When removing: flags=600, drv->flags=0, err=-129 Sending event 6/(unknown) to spy 'efi_disk del' eth1_mdio_mx-0: When removing: flags=600, drv->flags=0, err=-129 Sending event 6/(unknown) to spy 'efi_disk del' eth1_rgmii_mx-0: When removing: flags=600, drv->flags=0, err=-129 Sending event 6/(unknown) to spy 'efi_disk del' sdmmc1_mx-0: When removing: flags=600, drv->flags=0, err=-129 Sending event 6/(unknown) to spy 'efi_disk del' usart6_mx-0: When removing: flags=600, drv->flags=0, err=-129 pinctrl@44240000: When re

Dear all,We have a design where the VCCQ of eMMC is currently 3.3V. We need to move to 1.8V to be able to use a new referenceIs there any risk to break somthing if I use the below DTS on board where eMMC is 3.3V VCCQ. We have pull up to VCCQ on D0 and CMDvqmmc-supply = <&v1v8>; mmc-ddr-1_8v;According to my tests, system is up and running, but I fear this should have an impact on MPU padsIf no risk, this could avoid me to add a DTS overlay according to my hardware board version in case of 3.3V VCCQI add my layout for eMMC for better understanding, see R353 and R356 to switch VCCQThanks in advance for answers and hintsRegardsLaurent  

Hi!I have a STM32MP257F processor. The clock for SDMMC1 is constant at 3.3V. Therefore the U-boot cannot read the SD-card.My question is: What clock need to be active/chosed in the device tree so it u-boot can read the SD-card sdmmc1? Hit any key to stop autoboot: 0 Boot over mmc0! Saving Environment to MMC... stm32_sdmmc2 mmc@48220000: stm32_sdmmc2_getcd called stm32_sdmmc2 mmc@48220000: bus_with = 1, clock = 0 stm32mp25_reset clock-controller@44200000: reset id=69 offset=0x830 bit=0 status=1 stm32mp25_reset clock-controller@44200000: reset id=69 offset=0x830 bit=0 status=0 D/TC:? 0 tee_ta_init_session_with_context:562 Re-open trusted service a8cfe406-d4f5-4a2e-9f8d-a25dc754c099 F/TC:? 0 pta_scmi_invoke_command:404 SCMI command 0x3 ptypes 0x3 F/TC:? 0 pta_scmi_invoke_command:404 SCMI command 0x4 ptypes 0x651 F/TC:? 0 regulator_disable:142 v3v3 D/TC:? 0 tee_ta_close_session:465 csess 0x8212f890 id 1 D/TC:? 0 tee_ta_close_session:484 Destroy session D/TC:? 0 tee_ta_init_session_wi

The project requirement is to use optical ethernet with STM32MP257F. I want to try this interfacing first at STM32MP257F EV1 with some copper to optical Ethernet converter module, but in STM32MP257F EV1, Ethernet pins are not available for interfacing. Kindly suggest some solution for using optical ethernet with STM32MP257F.     Kindly send the solution as early as possible.     Thank you With Best Regards, Dr. Amruta S. Dixit

Hello,I am following AN4803 to simulate my board with an STM32MP151 with DDR3L memory, but there seems to be a problem with the IBIS model. These IBIS models have missing receiver voltage thresholds, which may affect analysis:IBIS File: C:\Users\...\IBIS\stm32mp151_153xaa_lfbga448_sm.ibsIBIS Model: MSD_D3RP3L_48Model does not have a [Receiver Thresholds] section.Only Vinh and Vinl thresholds are specified in the [Model Spec] section, and will be used for both AC and DC thresholds.Net: $9I75\DDR_DQ0Controller pin: U1.E21 (DDR_DQ0)Net: $9I75\DDR_DQ1Controller pin: U1.F21 (DDR_DQ1)Net: $9I75\DDR_DQ2Controller pin: U1.H21 (DDR_DQ2)Net: $9I75\DDR_DQ3Controller pin: U1.E20 (DDR_DQ3)Net: $9I75\DDR_DQ4Controller pin: U1.J21 (DDR_DQ4)Net: $9I75\DDR_DQ5Controller pin: U1.H20 (DDR_DQ5)Net: $9I75\DDR_DQ6Controller pin: U1.H22 (DDR_DQ6)Net: $9I75\DDR_DQ7Controller pin: U1.G19 (DDR_DQ7)Net: $9I75\DDR_DQ8Controller pin: U1.N22 (DDR_DQ8)Net: $9I75\DDR_DQ9Controller pin: U1.R21 (DDR_DQ9)Net: $9I75

I am using the STM32MP131 in a baremetal environment. Since there is no internal flash, I am planning to use external flash and DDR.I have confirmed that writing to and reading from the flash works, but I don't know how to start from FLASH instead of SYSRAM when powering on.I saved the FW's bin data at address 0 of the Flash and tried changing the boot mode to QUADSPI Flash, but it did not work.I think QUADSPI needs to be activated before reading and executing from Flash. Where should I activate this?Do I also need to modify the linker script for the firmware that runs from Flash? Please let me know if you have any solutions to this problemThank you very much in advance.

Hi,I’m working with a MYIR MYD-YA157C (STM32MP157AAC) board and I’m trying to restore a board using STM32CubeProgrammer (USB / DFU mode) with a FlashLayout TSV.The board is custom made , but the HW should not be a problemBut i am running into erorr: 16:47:55 : Download in Progress:16:47:56 : Error: failed to download Sector[0]16:47:56 : Error: failed to download the File16:47:56 : Error: Download partition 0x21 failed16:47:56 : Error: TSV flashing service failed16:47:56 : Disconnected from device. Little bit of a backgroundThe chip comes with preloaded yocto , and after trying to flash our distro we get this erorr  I tried the following thingsRemove everything from the EMMC - Nothing helpsChaning offsets - Did not helpUse UDF tool - Did not helpTried on different computer - Did not helpTried different cable  - Did not help It is very strange I attached logs from Cube programmer @Aimen1  Could somebody help us with some suggestions

I am working with the STM32MP257F-DK using the official Starter Package. Suddenly, the board entered a state where several power rails are disabled. The ST-LINK LED (LD5) is blinking red slowly, and there is no HDMI output (0V on the rail) I have SSH access via USB OTG (usb0), but the system is in a "degraded" state.The ST-LINK is not recognized by the PC.HDMI monitor detects no signal. Diagnostic Data (Output of grep "" /sys/class/regulator/*/state): I have attached a screenshot, but here are the critical regulators currently in disabled state:regulator.11 (vdd3v3_usb) -> disabledregulator.12 (v5v_hdmi) -> disabledregulator.3 (vddio3) & regulator.4 (vddio4) -> disabledregulator.7 (vddcore) -> disabled (Surprisingly, since the CPU is running).Attempts to fix: Tried to enable them via sysfs: echo enabled > /sys/class/regulator/regulator.12/state -> Result: Permission denied.Tried to force it via I2C: i2cset -f -y 0 0x33 0x93 0x01 -> Result: Write

For the STM32MP135 series, specifically the STPMIC1A I'm using, can VDD_CORE and VDD_CPU share the same power rail (buck1)?

My device is quite power-sensitive. If I use a single DDR3L module with an STM32MP157 or 135, can I eliminate the need for a VTT power supply?

Dear ST Community,I am currently working on a custom hardware design based on the STM32MP157CAC3 MPU, which includes LPDDR3 memory (Micron MT52L256M32D1PF) and multiple high-speed interfaces.As part of my signal integrity and high-speed design validation process, I need simulation models to conduct accurate analysis.I want to request the following:IBIS models for STM32MP157CAC3, specifically covering:1. DDR interface (LPDDR2/LPDDR3 controller)2. SDMMC interface3. Any other relevant high-speed I/Os(MIPI, LTDC, DCMI, SDMMC)S-parameter models (if available) for:1. High-speed I/O buffers2. DDR interface pins or PHYAny additional resources that may support SI/PI analysis, such as:1. IBIS-AMI models (if available)2. Reference simulation setups3. Application notes related to DDR signal integrityProject details:Custom PCB (not a direct copy of STM32MP1 DK2)LPDDR3 operating btw 300 - 800 MHzGoal: Pre-layout and post-layout SI validation (HyperLynx/ADSI understand that some of these models may r

Product:MCU/SoC: STM32MP2Description:In our ST Linux environment, the hantro-vpu driver registers:/dev/video5 -> VDEC (H.264/VP8 Decoder)/dev/video6 -> VENC (H.264/VP8 Encoder) We want to implement direct V4L2 API usage for H.264/VP8 encoding and decoding, without using GStreamer.Specific Questions: Are there official minimal examples or demos using pure V4L2 API for H.264 / VP8 encoding/decoding?DMA Usage: Is it possible to use DMA for input/output buffers in V4L2 mem2mem mode on STM32MP2 Hantro VPU? If yes, what is the recommended configuration and constraints? 

Is it okay to use the following connection for eMMC memory on the STM32MP157AAB3?Also, is it possible to set the eMMC memory to boot mode with this connection?PB14:SDMMC2_D0PB15:SDMMC2_D1PB3:SDMMC2_D2PB4:SDMMC2_D3PB8:SDMMC2_D4PB9:SDMMC2_D5PC6:SDMMC2_D6PC7:SDMMC2_D7PC1:SDMMC2_CKPG6:SDMMC2_CMD