STM32 MPUs

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Hello, I am trying to load a kernel driver (.ko file) for a MIPI camera I would like to use with the STM32MP257F-DK. It's for the imx664, and no driver is present already. I have the source for the driver, and was able to compile it into a .ko file, cross-compiled with the exact same OS as is present on the board and with the SDK set up as required. The vermagic line matches exactly: vermagic: 6.6.78 SMP preempt mod_unload aarch64However, every time I try and load the driver with insmod, with or without -f, I get the error: insmod: ERROR: could not insert module imx664.ko: Invalid module formatI am struggling to find where the incompatibility could be, since I have re-tried it a few times and been careful to set it up as ST's documentation says and also to match what is expected by the board. Is there something I am missing with this?

I have an issue were the Linux kernel is booting, then it just stops printing out messages from USART6.Meanwhile, optee, u-boot and TF-a is printing out messages from USART6. But not Linux after a while.What can have caused this?My processor is: STM32MP257F.

Hi,I'm working on to get the multiple SAI to Codec to work synchronized as the connection below,1x MCLK1x BCLK1x FSYNC4x DIN4x DOUTWhere the three Clocks 1x lines (MCLK, BCLK & LRCLK) from one SAI master (actual pinout clock) & other SAI (pinout DIN & DOUT) sync clock internally (not sure possible b/w the SAI).SAI1 (clock master) -> MCLK, BCLK, FSYNC, DIN/DOUT -> codec1SAI2 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec2SAI3 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec3SAI4 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec4According to the TRM RM0436 Rev 7 55.4.4 External synchronization should be used between the SAI.does this need external pin connection between two SAI (all three clocks)? I'm facing error when arecord on SAI1 in the background and trying to start playback on SAI2, attached dts overlay filearecord -D hw:0,0 -f S16_LE -r 48000 -c 2 -d 0 /dev/null &sleep 1aplay -D hw:0,2 -f

Hi!I having some issues with Linux at startup. It seems that it disabling the Bucks/LDOs at startup.vddio2: disabling vddio3: disabling vddio4: disabling vddcore: disabling v1v8: disabling v3v3: disablingWhy does this occur?Here is the complete output as attached file. As you can see, I have set up my own outputs for error handling. The device three can be found here:https://github.com/DanielMartensson/Watermelon-Wine-1A/tree/linux-testing/watermelon-wine-os%2Fcubemx%2FCA35%2FDeviceTree%2FfirmwareGood to know:clk_get_index = 143 is USART6.I have activated the RNG for TF-A only. It seems not to wake up. It's the same default configuration as DK. 

I have been working on porting a custom board using the STM32MP255F-AK.I performed the following tasks:- Used STMCubeMX to configure pins and other settings- Manually added the custom board-specific sections to the DeviceTree- Added the DeviceTree to the Distribution Package's meta-st/meta-stm32mp-addons/mx directory- Created a custom board configuration file and performed the build- Wrote the resulting TF-A and FIP images to an SD card and booted the system- Before performing this work, I verified the operation of STOpenLinux, which was created by modifying the STM32MP257F-DK Device TreeThe TF-A boots, but just before U-Boot starts, a register dump occurs repeatedly and the system stops progressingJudging by the error details, it appears to be a security-related error.Based on the address where the error occurred and the error ID,I tried making various changes to the .ioc and DT files, but the issue persisted.I suspect it’s a simple configuration mistake...What specific areas should I

Hello,I want to know what is the latest Chromium version supported by OpenST Linux on Scarthgap.Do we have GPU acceleration on it?Thank you in advance,Hiba @PPAGE.13@Billy OWEN @Gregory PLANCHON 

Dear all I was setting up the RISAF4 for STM32MP257, however, the partition with name "linuxkernel2" has a glitch where its size shows as givenWhich is beyond the size of my LDDR4 set to 8Gb.How to solve it? A quick reply will be appreciated.Thanking you!With regardsAmit 

Dear ST Team,I Need the clarification can I use YT9218MB in place of RTL8211F-CG ,Please recommend me , If we can then we need to use OpenWRT

Hi everyone,I'm currently validating a custom board featuring the STM32MP257 interfacing a single 16-bit DDR4 at 2133MT/s (Point-to-Point topology). I am using the ST-provided Excel tool ("Examples of DDR memory routing on STM32MP2 MPUs") to extract the Die-to-Ball Package Trace Lengths (mm).I’ve run into a few specific SI conflicts regarding the hardware guidelines, primarily driven by my PCB stackup. Due to routing density, my Address/Command (A/C) signals are split across two different layers:L6 (Bottom Layer): Microstrip. Outer solder mask is 0.6mil (Dk 4.85) over a 3.91mil 3313 Prepreg (Dk 4.4). Effective Dk is much lower due to air exposure.L3 (Inner Layer): Stripline. Sandwiched between a Core (Dk 4.6) and Prepreg (Dk 4.5). Effective Dk is approx 4.5.This leads to the following questions:1. Balancing Physical Length (mm) vs. Electrical Delay (ps): The ST guideline dictates an A/C to CLK_P/N equalization of +/- 140 mils (3.55 mm). However, if I strictly match the physical length

I am trying to build a custom Yocto Scarthgap image for a custom STM32MP153CAA3 board.I have followed the guide at https://wiki.st.com/stm32mpu/index.php/How_to_create_your_own_machine but have several issues.I have created a configuration in CubeMX 6.15.0 and exported the DTB into my project.When I try and build I get an error in u-boot ERROR (phandle_references): /soc/rcc@50000000: Reference to non-existent node or label "clk_hse"(along with references to other clock nodes)I do a `devtool  modify u-boot-stm32mp`  to get at the source code and follow through the DTB The includes from the u-boot DTB file from CubeMX are:#include "stm32mp153.dtsi" #include "stm32mp15xa.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" #include "stm32mp15-m4-srm.dtsi" #include "stm32mp15-scmi.dtsi"stm32mp153.dtsi includes stm32mp151.dtsi which references the clocks, which is great.However the last include, stm32mp15-scmi.dtsi then goes and deletes them all!/delete-node/ &clk_h

Hello,coming from OpenSTLinux 4.2 (mickledore) we are in the process of migrating to OpenSTLinux 6.2 (scarthgap).The process of how multiple partitions (bootfs, vendorfs, userfs) are "split out" of the rootfs appears to have changed considerably.After switching all relevant meta layers to the commit/version used in OpenSTLinux 6.2, we effectively get bitbake QA errors for every image recipe (even the ones not being built). The errors appear related to the new bbclass "stsplitpartitions".The release notes of OpenSTLinux 6.2 mention the change as "Add image class to split rootfs image on several partitions: ST SPLIT PARTITIONS", but fail to provide any guideline on how to migrate existing projects to the new partitioning scheme.For testing, I removed all our proprietary layers and only kept the ST layers and standard Bitbake/OpenEmbedded layers.But the errors persist even for this minimal setup when building the standard ST image recipe st-image-core.How does st-split-part

Hi,I recently just finished the Yocto Bringup of a custom STM32MP15FAA1. Everything seems to be working in my application. I am now looking to begin development of the M4 in which I need access to either SWD or JTAG to do lower-level development. Unfortunately, I am having trouble connecting to either interfaces through both CubeIDE and also manually inputting OpenOCD in an IDF Powershell instance.I presume the easiest way to get to my goal is to setup SWD which on the MP15 maps to TMS (SWDIO) and TCLK (SWCLK) and I connected GND and VCC. My STLinkV3-MIME detects 3.3V on the reference line but can never connect to target. This is my first time working with a SOM as most of my development is on base Cortex M microcontrollers so I have a few questions.1. Is there anything in the M4 device tree that can be preventing JTAG from operating like the STPMIC? I do have M4 RPROC enabled in my device tree and the file descriptor is available for me to access.2. Does the boot mode matter? My end a

Hi!I think a have found a bug in CubeMX for STM32MP257F processor.If you go to RIF - RISAB - VDERAM. You will find that the region size can only be 0x21000. That's more than 128 kB, according to the data sheet.SYSRAM1, SYSRAM2, SRAM1, SRAM2, RETRAM have 0x20000 as maximum region size.Question: If this is a bug, then I want to send a PR to the Github ST repository of the MP2 firmware. Can you guide me where the code is so I can make a PR?

Hi,We are building Linux for STM32MP157D using Buildroot, and we are experiencing an issue where the boot process sometimes does not proceed from BL2 to OP-TEE, and sometimes OP-TEE does not proceed to U-Boot.Occasionally, the kernel does boot successfully.Could this be caused by incorrect DDR3 controller settings? We are using a custom board.If so, would compiling the STM32DDRFW-UTIL source code and using it in engineering mode be the right solution?I have read that for some chips it is possible to perform automatic tuning and receive the optimal configuration as a result.Is this possible in this case? If not, what is the proper method to determine the correct DDR controller settings?If DDR is not the issue, do you have any other suggestions?For testing with DDR-UTIL, I see that there is no development board listed for the 157D series, as the utility supports "STM32MP157C-EV1_DDR_UTILITIES_A7".If we order the "STM32MP157D-EV1", will I be able to run DDR tests on it to compare with our

Hi,i tried to migrate my project to CubeMx v6.17.0 coming from v6.16.0As a result, the firmware package was also updated to FW_MP1 V1.7.0I am using CubeIDE 2.0.0After migration the compilation fails with following error in auto-generated FreeRTOSConfig.hDescription Resource Path Location Type each undeclared identifier is reported only once for each function it appears in FreeRTOSConfig.h /PROJECT_CM4/Inc line 71 C/C++ Problem/* USER CODE BEGIN Header */ /* * FreeRTOS Kernel V10.6.2 * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Softw

Hello STM Team,I have been trying to get the GC2145 to work on the DK but no matter what i do i only get /dev/video0 but never /dev/media0I use Buildroot with the Linux kernel on ST's Github. I have followed this guide here: https://wiki.st.com/stm32mpu/wiki/STM32MP13_V4L2_camera_overview and i have all the Kernel modules needed activated.I know the camera is plugged in properly because the demo from ST works but there's no code or config that goes along that demo for me to find the issue, at least i could not find it.I will attach a little bit of debug info at the bottom if its any helpful:# dmesg | grep -i gc2145 [ 0.058299] /soc/bus@5c007000/i2c@4c006000/stmipi@14: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@4c006000/gc2145@3c [ 0.058443] /soc/bus@5c007000/i2c@4c006000/gc2145@3c: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@4c006000/stmipi@14 [ 0.069826] /soc/bus@5c007000/i2c@4c006000/stmipi@14: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@4c006000/gc2145@3c

Hi everybody,For a project, we need to start the STM32MP257F in the M33 flavor, in order to perform some basic functions (GPIO, I2C, UART) in the lowest power mode possible (DDR unpowered, A35 in low power mode — i.e., no remoteproc nor Linux). The goal is to compare MP257 capabilities compared to IMX8 (goal line end of this month)I use Yocto/bitbake to compile for our custom board.Following the StarterApp_M33TD_CM33 example, I've encountered the following difficulties:1) How can I debug the BL2 part?From the post STM32MP257 programming via JTAG - STMicroelectronics Community , I see that JTAG can be used to debug the STM32MP257 using CubeIDE.2) How can this be done?I tried to modify the *.ld file used by StarterApp_M33TD_CM33 to place the code in internal RAM instead of DDR, but it doesn't work. On the UART console I see BL2 logs, but nothing from this app, and since I can't debug, I don't know what's happening.3) How do I modify the project/Device Tree or other elements to execu