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OKN
Associate III
April 17, 2026
Question

[STM32MP255F] SERC exception occurs during boot

  • April 17, 2026
  • 1 reply
  • 93 views

I have been working on porting a custom board using the STM32MP255F-AK.

I performed the following tasks:

- Used STMCubeMX to configure pins and other settings
- Manually added the custom board-specific sections to the DeviceTree
- Added the DeviceTree to the Distribution Package's meta-st/meta-stm32mp-addons/mx directory
- Created a custom board configuration file and performed the build
- Wrote the resulting TF-A and FIP images to an SD card and booted the system
- Before performing this work, I verified the operation of STOpenLinux, which was created by modifying the STM32MP257F-DK Device Tree

The TF-A boots, but just before U-Boot starts, a register dump occurs repeatedly and the system stops progressing

Judging by the error details, it appears to be a security-related error.
Based on the address where the error occurred and the error ID,
I tried making various changes to the .ioc and DT files, but the issue persisted.

I suspect it’s a simple configuration mistake...

What specific areas should I check carefully?

 

NOTICE: CPU: STM32MP255FAK Rev.Y
NOTICE: Model: STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06
NOTICE: Reset reason (0x2035):
INFO: Power-on Reset (rst_por)
INFO: PMIC2 version = 0x11
INFO: PMIC2 product ID = 0x21
INFO: FCONF: Reading TB_FW firmware configuration file from: 0xe011000
INFO: FCONF: Reading firmware configuration information for: stm32mp_fuse
INFO: FCONF: Reading firmware configuration information for: stm32mp_io
INFO: Using SDMMC
INFO: Instance 1
INFO: Boot used partition fsbl1
NOTICE: BL2: v2.10-stm32mp2-r1.0(debug):devtool-patched(2ba93b6f)
NOTICE: BL2: Built : 04:18:10, Apr 13 2026
INFO: BL2: Loading image id 26
INFO: Loading image id=26 at address 0xe041000
INFO: Image id=26 loaded: 0xe041000 - 0xe049650
INFO: BL2: Doing platform setup
INFO: RAM: LPDDR4 32bits 1200000kHz
INFO: Memory size = 0x80000000 (2048 MB)
INFO: BL2: Loading image id 1
INFO: Loading image id=1 at address 0xe000000
INFO: Image id=1 loaded: 0xe000000 - 0xe000326
INFO: FCONF: Reading FW_CONFIG firmware configuration file from: 0xe000000
INFO: FCONF: Reading firmware configuration information for: risaf_config
INFO: RISAF2: No configuration in DT, use default
INFO: FCONF: Reading firmware configuration information for: dyn_cfg
INFO: BL31 max size = 0x17000 (94208B)
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xe000000
INFO: Image id=3 loaded: 0xe000000 - 0xe0167c0
INFO: BL2: Loading image id 19
INFO: Loading image id=19 at address 0x81fc0000
INFO: Image id=19 loaded: 0x81fc0000 - 0x81fc39e6
INFO: BL2: Loading image id 4
INFO: Loading image id=4 at address 0x82000000
INFO: Image id=4 loaded: 0x82000000 - 0x8200001c
INFO: OPTEE ep=0x82000000
INFO: OPTEE header info:
INFO: magic=0x4554504f
INFO: version=0x2
INFO: arch=0x1
INFO: flags=0x0
INFO: nb_images=0x1
INFO: BL2: Loading image id 8
INFO: Loading image id=8 at address 0x82000000
INFO: Image id=8 loaded: 0x82000000 - 0x820fc628
INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0x84400000
INFO: Image id=2 loaded: 0x84400000 - 0x844188d0
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x84000000
INFO: Image id=5 loaded: 0x84000000 - 0x841c49b8
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xe000000
INFO: SPSR = 0x3cd
INFO: ARM GICv2 driver initialized
NOTICE: BL31: v2.10-stm32mp2-r1.0(debug):devtool-patched(2ba93b6f)
NOTICE: BL31: Built : 04:18:10, Apr 13 2026
INFO: BL31: Initializing runtime services
INFO: BL31: Initializing BL32
I/TC: Early console on UART#2
I/TC:
I/TC: Embedded DTB found
I/TC: OP-TEE version: devtool-patched (gcc version 13.3.0 (GCC)) #5 Mon Apr 13 02:56:36 UTC 2026 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: WARNING: All debug access are allowed
I/TC: Override the OTP 124: 0 to 0x18db6
I/TC: WARNING: Embeds insecure stm32mp_provisioning driver
E/TC:0 0
E/TC:0 0 Core data-abort at address 0x794e0ff0
E/TC:0 0 esr 0x96000210 ttbr0 0x82163000 ttbr1 0x00000000 cidr 0x0
E/TC:0 0 cpu #0 cpsr 0x800003c4
E/TC:0 0 x0 0000000082133fe0 x1 0000000000000000
E/TC:0 0 x2 00000000000076d0 x3 0000008000000000
E/TC:0 0 x4 0000000000000020 x5 0000000082133ff0
E/TC:0 0 x6 ffffffffffffffe0 x7 0000000000026e70
E/TC:0 0 x8 0000000000026e70 x9 000000008213cf30
E/TC:0 0 x10 000000008210d160 x11 0000000082164e3c
E/TC:0 0 x12 0000000000000001 x13 000000000000b4a8
E/TC:0 0 x14 0000000082164ea4 x15 00000000820a7900
E/TC:0 0 x16 0000000082031f20 x17 0000000000000000
E/TC:0 0 x18 0000000000000000 x19 0000000082134000
E/TC:0 0 x20 00000000820a7900 x21 000000000000b730
E/TC:0 0 x22 0000000000000000 x23 00000000794e0000
E/TC:0 0 x24 0000000000000001 x25 00000000820b3110
E/TC:0 0 x26 0000000000000001 x27 0000000080000000
E/TC:0 0 x28 0000000000000000 x29 0000000082164ef0
E/TC:0 0 x30 000000008202f46c elr 000000008202f474
E/TC:0 0 sp_el0 0000000082164e70
E/TC:0 0 stm32_serc_handle_ilac:133 SERC exceptions [159:128]: 0x400
E/TC:0 0 stm32_serc_handle_ilac:139 SERC exception ID: 138
E/TC:0 0
E/TC:0 0 Core data-abort at address 0x794e0ff0
E/TC:0 0 esr 0x96000210 ttbr0 0x82163000 ttbr1 0x00000000 cidr 0x0
E/TC:0 0 cpu #0 cpsr 0x800003c4
E/TC:0 0 x0 0000000082133fe0 x1 0000000000000000
E/TC:0 0 x2 00000000000076d0 x3 0000008000000000
E/TC:0 0 x4 0000000000000020 x5 0000000082133ff0
E/TC:0 0 x6 ffffffffffffffe0 x7 0000000000026e70
E/TC:0 0 x8 0000000000026e70 x9 000000008213cf30
E/TC:0 0 x10 000000008210d160 x11 0000000082164e3c
E/TC:0 0 x12 0000000000000001 x13 000000000000b4a8
E/TC:0 0 x14 0000000082164ea4 x15 00000000820a7900
E/TC:0 0 x16 0000000082031f20 x17 0000000000000000
E/TC:0 0 x18 0000000000000000 x19 0000000082134000
E/TC:0 0 x20 00000000820a7900 x21 000000000000b730
E/TC:0 0 x22 0000000000000000 x23 00000000794e0000
E/TC:0 0 x24 0000000000000001 x25 00000000820b3110
E/TC:0 0 x26 0000000000000001 x27 0000000080000000
E/TC:0 0 x28 0000000000000000 x29 0000000082164ef0
E/TC:0 0 x30 000000008202f46c elr 000000008202f474
E/TC:0 0 sp_el0 0000000082164e70
E/TC:0 0 stm32_serc_handle_ilac:133 SERC exceptions [159:128]: 0x400
E/TC:0 0 stm32_serc_handle_ilac:139 SERC exception ID: 138
E/TC:0 0
E/TC:0 0 Core data-abort at address 0x794e0ff0
E/TC:0 0 esr 0x96000210 ttbr0 0x82163000 ttbr1 0x00000000 cidr 0x0
E/TC:0 0 cpu #0 cpsr 0x800003c4
E/TC:0 0 x0 0000000082133fe0 x1 0000000000000000
E/TC:0 0 x2 00000000000076d0 x3 0000008000000000
E/TC:0 0 x4 0000000000000020 x5 0000000082133ff0
E/TC:0 0 x6 ffffffffffffffe0 x7 0000000000026e70
E/TC:0 0 x8 0000000000026e70 x9 000000008213cf30
E/TC:0 0 x10 000000008210d160 x11 0000000082164e3c
E/TC:0 0 x12 0000000000000001 x13 000000000000b4a8
E/TC:0 0 x14 0000000082164ea4 x15 00000000820a7900
E/TC:0 0 x16 0000000082031f20 x17 0000000000000000
E/TC:0 0 x18 0000000000000000 x19 0000000082134000
E/TC:0 0 x20 00000000820a7900 x21 000000000000b730
E/TC:0 0 x22 0000000000000000 x23 00000000794e0000
E/TC:0 0 x24 0000000000000001 x25 00000000820b3110
E/TC:0 0 x26 0000000000000001 x27 0000000080000000
E/TC:0 0 x28 0000000000000000 x29 0000000082164ef0
E/TC:0 0 x30 000000008202f46c elr 000000008202f474
E/TC:0 0 sp_el0 0000000082164e70
E/TC:0 0 stm32_serc_handle_ilac:133 SERC exceptions [159:128]: 0x400
E/TC:0 0 stm32_serc_handle_ilac:139 SERC exception ID: 138
E/TC:0 0

**The same register dump and error message keep appearing...**

 

 

 

1 reply

Erwan SZYMANSKI
Erwan SZYMANSKI
Technical Moderator
April 21, 2026

Hello @OKN ,
A SERC error is commonly an issue caused by using an IP when it is not well clocked. (see this article: https://wiki.st.com/stm32mpu/wiki/How_to_analyze_IAC_%26_SERC_errors#SERC_debug)

According to the table present in the Reference manual, ID 138 corresponds to RISAF5.

We need now to understand what happens in your case.

According to your logs, U-Boot has not started yet. We are still in OP-TEE boot sequence (TF-A BL31 first starts OP-TEE, then jump to U-Boot).

Could you please share your OP-TEE device tree used in your system ?

Kind regards,
Erwan.

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O
OKNAuthor
Associate III
April 21, 2026

Hello @Erwan SZYMANSKI 

Thank you for your reply.

I have attached the OP-TEE DeviceTree.

I reviewed the RIF settings and other configurations in STMCubeMX, but the issue remains unresolved...

Best regards,
---
OKN

Erwan SZYMANSKI
Erwan SZYMANSKI
Technical Moderator
April 22, 2026

Hello @OKN ,
For test purpose, and to check if this is not an IAC that has a SERC side effect, could you please in OP-TEE, in clk-stm32mp25.c file, add the flex34 as a clock_critical (there is a table with a list of clock inside).

Then tell me if your error log changed.

Kind regards,
Erwan.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
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