How can I set the timer to trigger ADC on counter overflow?

[NTosi]

Hi,

I have set the timer4 in center alligned mode 3 and I want to trigger ADC on counter overflow. If I understand correctly the ADC trigger input TIM4_TRGO can be set in timer configuration as update event output but that means also in underflow will send the timer a trigger for conversion.

Do you know any solution?

[GwenoleB]

Dear @NTosi​,

Indeed, ADC cannot differentiate a counter overflow or underflow as the trigger is common.

The UEV Update Event is set when an overflow or underflow occurs, then the trigger will be set also to the ADC.

To understand better your application, is there any reason you use the center aligned mode on TIM4?

Best Regards,

Gwénolé

[NTosi]

Hi,

thank you for your reply. I try to implement a FOC algorithm and I have seen also some application notes from ST, in which they mentioned this process for better adc measuring.

[GwenoleB]

Hello,

Alright! Will be possible to provide the MCU reference you are using?

It could be useful to verify embedded features inside the TIM4.

Best Regards,

Gwénolé

[NTosi]

Hi,

I use F446RE and my configurations is like TIM1 -> is a master with CH1 and CH1N also CH2 CH2N are used for the phase U and V. The TIM4 is the slave and is synchronized with TIM1 and is connected with phase W.

The TIM1 has the TRGO as a Counter Enabled output so I cannot use it for the PWM.

Right now I use the CH1N to trigger the ADC conversion but I have seen in STM application note that if I change to counter overflow I can have a better result.

best regards,

Nikos

[GwenoleB]

Hi,

Indeed two solutions exist:

1. Trigger the ADC on OCxREF signal meaning that ADC trigger is 90° out of phase with Overflow flag
2. Cascade a third timer to generate a trigger on ADC. This timer is a slave of the TIM1 also.

Below a scheme of how timers and ADC are interconnected

 

TIM1 & TIM4 are setup as center aligned 3 (Up and Down CNT).

TIM3 is setup as Up CNT where ARR = 2*(ARR_TIM1)-1. Be sure that ARR of TIM1 doesn't exceed 65536/2, else we recommend the usage of TIM2/5 (32-bit resolution).

Please note that:

• TIM2/3/8 can be used to trigger ADC for regular conversion
• TIM2/5 for injected conversion. For TIM5, it must be triggered by TIM4 CNT_EN in aid of TIM1

Blue --> PWM signal

Red --> End of ADC conversion (IO toggling)

As a result, ADC will be synchronized with Overflow of TIM1 & TIM4

Let me know if it's unclear or you need more clarification.

Best Regards,

Gwénolé

[NTosi]

Thank you, top support!

I will test it the next days and I will be back to write the results.

best regards,

Nikos

[GwenoleB]

Hello @NTosi​,

Will you able to share your ADC configuration? Based on this I will guide you on TIM configuration.

Nevertheless, using injected conversion requires the use of TIM2 or TIM5 in aid of TIM3 as depicted in my previous scheme.

In the Reference Manual, you will find the list of signals able to trigger the ADC in injected mode:

At least, you need to select a TIMx_TRGO event and not a TIMx_CHy event.

Anyway, feel free to share with your ADC configuration and I will help you with TIMER configuration.

Best Regards,

Gwénolé

[NTosi]

Hi,

I made the changes and is working BUT not properly. The timer 1 has ARR = 500 and the timer 2 as you said ARR = 999 but the ADC will be triggered when the PWM output is HIGH. (I use tim2 because tim3 is occupied).

But this is not what I want, because in FOC algorithm the ADC Conversion should be start when the Low Side of the Bridge is high.

The first build is how I understand this and the second of the oscilloscope, the blue is the ADC interrupt and the other are the two synchronized timers.

 

[NTosi]

Hi, 

I didn't received any Feedback, I found a workaround for my issue but I would like to review with you and be sure that is not a bug in hardware or I am wrong, could you help me?