Several issues on STM32U0, STM32F0 and STM32G0 documentation.
As I said before, several issues mentioned in post https://community.st.com/t5/stm32-mcus-products/missing-section-irtim-in-stm32u0-rm-and-more/td-p/667127, were not fixed.
And I have more.
STM32F0:
1. RM0091 page 184 and table 27: Missing SYSCFG_ITLINE31 register with USB bit.
2. RM0091 page 629: There is a register RTC_OR with RTC_ALARM_TYPE and TSINSEL[1:0] bits. But it is missing register description before section "25.7.17 RTC backup registers (RTC_BKPxR)". On STM32L0 RM this register is named "RTC option register".
3. RM0091 page 613: "This register is write protected (except for RTC_ISR[13:8] bits)." Bits [13:8] should be [15:8].
STM32G0:
1. RM0444 page 165: Register RCC_AHBSMENR should be RCC_BDCR.
2. RM0444 page 75: Mentions HPREF bit, but it doesn't exist.
STM32U0:
1. RM0503 page 162: Register RCC_AHBSMENR should be RCC_BDCR.
2. RM0503: Missing IRTIM IR_POL bit in SYSCFG_CFGR1 register.
3. RM0503 page 61: TIM1/15 should be TIM1/15/16.
4. RM0503 page 64, typo: '32 bytes x 72 bits' should be '32 Kbytes x 72 bits'.
5. RM0503 page 67: Mentions HPREF bit, but it doesn't exist.
6. RM0503 page 153: 64 MHz should be 56 MHz. Page 497: 54 MHz should be 56 MHz.
7. RM0503 page 57 table 2 continues with wrong addresses. Also 0x0008 0000 should be 0x0004 0000.
8. STM32U0 only have USB device mode but host mode is also in RM0503.
9. RM0503 page 56, figure 2: It is missing IOPORT address. See STM32G0 RM.
10. RM0503 page 72: 'The 16 double words must be written successively' should be 'The 32 double words must be written successively'.
11. RM0503 page 705, table 135: I think missing ITR3 is TIM16_OC1.
12. RM0503 page 413: Missing TRIM[5:0] description. See STM32G0 RM.
13. RM0503 page 411: Missing
VRS = 0: VREF_OUT1 around 2.048V
VRS = 1: VREF_OUT2 around 2.5V
See STM32G0 RM.
14. RM0503 page 67, typo: c o c k (without spaces) should be clock.
15. DS page 79, PLL characteristics: 64 MHz. 64 MHz should be 56 MHz
16. DS: Missing I2C3 pins in Boot modes section.
17. DS page 24: 'keeping 20 bytes' should be '36 bytes' because STM32U0 have 9 32-bit backup registers.
18. DS page 23: 'nine 32-bit backup registers'. It is better if this is '9 32-bit backup registers'.
19. AN6226 have several errors. STM32U0 doesn't have FDCAN. NVIC table is wrong. STM32U0 doesn't have TIM17 and have TSC, LCD and I2C4.
20. Have STM32U0 backup SRAM powered through the VBAT pin? I Think the answer is no. But...
20.1. AN5938 page 5: The backup SRAM is optionally powered through the VBAT pin, when the BREN bit is set in PWR_BDCR1.
20.2. AN5938 page 8, figure 2: VBAT backup SRAM.
20.3. AN5938 page 3 and 11: Backup SRAM.
20.4. RM0503 page 105, figure 6: 'SRAM2 (optional)' is powered by VBAT.
20.5, I think there are more cases where SRAM2 powered by VBAT is mentioned.
21. AN5938 page 15: Mentions TIM15/TIM16/TIM17. But TIM17 doesn't exist.
22. RM0503 bookmarks:
35 Low-power universal asynchronous receiver transmitter
To be like the other sections, should be:
35 Low-power universal asynchronous receiver transmitter (LPUART)
23. RM0503 page 249: Missing IWDG bit in SYSCFG_ITLINE0 register.