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qua
Associate III
April 5, 2026
Question

STM32 with at least 8 DMA channels that can be triggered by and write to GPIOs

  • April 5, 2026
  • 4 replies
  • 378 views

Hi.

I'm looking for an STM32 with a lot of GPIO triggered DMA channels. I need 8 channels that trigger when a pin changes state, and which can read/write to GPIO registers and DMA registers.

It's for implementing a bus interface where I need to read address pins and write them into the lower 16 bits of DMA address registers, and use pin transitions to trigger GPIO state changes (GPIO data values, GPIO direction bits).

Are there any parts that can do that? The M0+ series doesn't have enough DMA channels that can be triggered by GPIOs. The M3 and M4 doesn't seem to allow triggering from GPIOs.

4 replies

MM..1
Chief III
April 5, 2026

Your explain is little chaos. For triggering is designed EXTI NVIC not DMA.

qua
quaAuthor
Associate III
April 5, 2026

I want to trigger 8 DMA channels from GPIO pins. On an M0+ you only get 4 DMA channels that can be triggered by EXTI pins.

Are there any STM32 parts that have more DMA channels that can be triggered by GPIOs/EXTIs?

TDK
Super User
April 5, 2026

Pretty sure chips with DMAMUX like the H7 can trigger DMA from pin events it with request generators. DMA to/from GPIO is slow, may not work for what you want. If you always want the same action in response to a rising/falling edge, it may work, but that seems very limited in functionality.

Timers may be a better choice.

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qua
quaAuthor
Associate III
April 5, 2026

I'm trying to interface with a Z80 bus to start with, and later some other CPUs. Basically I need to have a few DMA actions complete in 100ns. It's possible with interrupts and a very fast clock and assembler, but I'd rather avoid that.

Timers are a good idea. Input capture triggering DMA.

 

When the host CPU does a memory read

- Copy 16 address bits into lower 16 bits of DMA channel source address.

- Copy byte from RAM to data bus GPIO port lower 8 bits.

- Set data bus GPIO port lower 8 bits direction to output.

- Might need to set an external voltage translator direction pin, can do that by writing a GPIO with DMA.

- Release the bus at the end of the read cycle.

 

For sequencing I was going to try using DMA priorities with them all sharing a common trigger, but if that doesn't work then it's probably possible to chain clocks together to do it.

TDK
Super User
April 5, 2026

 

You're near the edge of what is possible. I'm not sure which side of the edge it falls on.

Be aware that even when you "write" to a GPIO in assembly, it takes some time for that to actually propagate to the pin and take effect. On more complex chips, this takes longer than on simpler ones. Same thing for reads. If states are only valid for 100ns I don't think it's going to be possible. Could be wrong.

It would be a fun project to try.

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qua
quaAuthor
Associate III
April 5, 2026

I know, it's certainly a contraption. Are GPIOs really that slow though? At say 180MHz you have 18 cycles in 100ns.

I've done a bit of high speed stuff with STM32. Admittedly nothing like this, but with timers triggering DMA that writes to a GPIO to generate a complex waveform (IRIG-B) it was pretty fast, maybe 40ns maximum latency with a 100MHz clock. I didn't dive too deep into it, it's possible that it's occasionally worse than that if one of the internal buses is busy.

TDK
Super User
April 5, 2026

Somewhere there is a thread looking at the maximum GPIO toggle rate using CPU instructions. For the H7, I think it's something like 8 MHz, despite the CPU being 400ish MHz.

It's not that the GPIO is slow, it's the busses needed to get from the CPU to the GPIO that take time. The path from DMA to GPIO may be quicker.

This is a dual core H7. Other chips are considerably different.

Screenshot 2026-04-05 115421.png

 

This is the G0 which has DMAMUX and the necessary triggers but the DMA doesn't have access to GPIOs so it won't work at all for you, I believe.

Screenshot 2026-04-05 115921.png

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Michal Dudka
Lead
April 8, 2026

In general, DMA can be triggered from pins using timers (either via TIMx_ETR or via TIMx_CHy).

If I remember correctly, you can only change the address in DMA if the channel is disabled. And so you have to enable it again afterward. While this can be done using another DMA channel, it will likely be a complication that ruins the whole solution.

Have you considered using FMC/FSMC?

qua
quaAuthor
Associate III
April 8, 2026

I think you are right, you can only change the DMA address with the channel disabled.

I did have a quick look at FMC and FSMC, but I think they can only be used as bus master.

I was hoping to use STM32 as I am familiar with them, but I think this calls for an RPi Pico.

mƎALLEm
Technical Moderator
April 8, 2026

Hello @qua ,

What about using PSSI interface?

Please refer to these knowledge base articles:

Do you need a fast slave interface with high throughput? This is for you.

How to configure and use the PSSI on the STM32H7

Overall FAQs for PSSI

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